/* * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre * Copyright (C) 2014 Robert Jarzmik * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ #define __DT_BINDINGS_CLOCK_PXA2XX_H__ #define CLK_NONE 0 #define CLK_1WIRE 1 #define CLK_AC97 2 #define CLK_AC97CONF 3 #define CLK_ASSP 4 #define CLK_BOOT 5 #define CLK_BTUART 6 #define CLK_CAMERA 7 #define CLK_CIR 8 #define CLK_CORE 9 #define CLK_DMC 10 #define CLK_FFUART 11 #define CLK_FICP 12 #define CLK_GPIO 13 #define CLK_HSIO2 14 #define CLK_HWUART 15 #define CLK_I2C 16 #define CLK_I2S 17 #define CLK_IM 18 #define CLK_INC 19 #define CLK_ISC 20 #define CLK_KEYPAD 21 #define CLK_LCD 22 #define CLK_MEMC 23 #define CLK_MEMSTK 24 #define CLK_MINI_IM 25 #define CLK_MINI_LCD 26 #define CLK_MMC 27 #define CLK_MMC1 28 #define CLK_MMC2 29 #define CLK_MMC3 30 #define CLK_MSL 31 #define CLK_MSL0 32 #define CLK_MVED 33 #define CLK_NAND 34 #define CLK_NSSP 35 #define CLK_OSTIMER 36 #define CLK_PWM0 37 #define CLK_PWM1 38 #define CLK_PWM2 39 #define CLK_PWM3 40 #define CLK_PWRI2C 41 #define CLK_PXA300_GCU 42 #define CLK_PXA320_GCU 43 #define CLK_SMC 44 #define CLK_SSP 45 #define CLK_SSP1 46 #define CLK_SSP2 47 #define CLK_SSP3 48 #define CLK_SSP4 49 #define CLK_STUART 50 #define CLK_TOUCH 51 #define CLK_TPM 52 #define CLK_UDC 53 #define CLK_USB 54 #define CLK_USB2 55 #define CLK_USBH 56 #define CLK_USBHOST 57 #define CLK_USIM 58 #define CLK_USIM1 59 #define CLK_USMI0 60 #define CLK_MAX 61 #endif e71b24440b5f1d93e968ee3'>refslogtreecommitdiff
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /include/math-emu/quad.h
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/math-emu/quad.h')