/*
* Copyright 2014 Ulrich Hecht
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
#define __DT_BINDINGS_CLOCK_R8A73A4_H__
/* CPG */
#define R8A73A4_CLK_MAIN 0
#define R8A73A4_CLK_PLL0 1
#define R8A73A4_CLK_PLL1 2
#define R8A73A4_CLK_PLL2 3
#define R8A73A4_CLK_PLL2S 4
#define R8A73A4_CLK_PLL2H 5
#define R8A73A4_CLK_Z 6
#define R8A73A4_CLK_Z2 7
#define R8A73A4_CLK_I 8
#define R8A73A4_CLK_M3 9
#define R8A73A4_CLK_B 10
#define R8A73A4_CLK_M1 11
#define R8A73A4_CLK_M2 12
#define R8A73A4_CLK_ZX 13
#define R8A73A4_CLK_ZS 14
#define R8A73A4_CLK_HP 15
/* MSTP2 */
#define R8A73A4_CLK_DMAC 18
#define R8A73A4_CLK_SCIFB3 17
#define R8A73A4_CLK_SCIFB2 16
#define R8A73A4_CLK_SCIFB1 7
#define R8A73A4_CLK_SCIFB0 6
#define R8A73A4_CLK_SCIFA0 4
#define R8A73A4_CLK_SCIFA1 3
/* MSTP3 */
#define R8A73A4_CLK_CMT1 29
#define R8A73A4_CLK_IIC1 23
#define R8A73A4_CLK_IIC0 18
#define R8A73A4_CLK_IIC7 17
#define R8A73A4_CLK_IIC6 16
#define R8A73A4_CLK_MMCIF0 15
#define R8A73A4_CLK_SDHI0 14
#define R8A73A4_CLK_SDHI1 13
#define R8A73A4_CLK_SDHI2 12
#define R8A73A4_CLK_MMCIF1 5
#define R8A73A4_CLK_IIC2 0
/* MSTP4 */
#define R8A73A4_CLK_IIC3 11
#define R8A73A4_CLK_IIC4 10
#define R8A73A4_CLK_IIC5 9
#define R8A73A4_CLK_IRQC 7
/* MSTP5 */
#define R8A73A4_CLK_THERMAL 22
#define R8A73A4_CLK_IIC8 15
#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */
f='/cgit.cgi/linux/net-next.git/refs/?h=nds-private-remove&id=c26665ab5c49ad3e142e0f054ca3204f259ba09c'>refslogtreecommitdiff
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in
the initrd since the first AP had already done that but it can also hurt
us:
Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for
example) which updates the microcode on the BSP but since the microcode
engine is shared between the two threads, the update on CPU1 doesn't
happen because it has already happened on CPU0 and we don't find a newer
microcode revision on CPU1.
Which doesn't set the intel_ucode_patch pointer and at initrd
jettisoning time we don't save the microcode patch for later
application.
Now, when we suspend to RAM, the loaded microcode gets cleared so we
need to reload but there's no patch saved in the cache.
Removing the optimization fixes this issue and all is fine and dandy.
Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading")
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>