/* * Copyright (C) 2016 Cogent Embedded Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ #include /* r8a7743 CPG Core Clocks */ #define R8A7743_CLK_Z 0 #define R8A7743_CLK_ZG 1 #define R8A7743_CLK_ZTR 2 #define R8A7743_CLK_ZTRD2 3 #define R8A7743_CLK_ZT 4 #define R8A7743_CLK_ZX 5 #define R8A7743_CLK_ZS 6 #define R8A7743_CLK_HP 7 #define R8A7743_CLK_B 9 #define R8A7743_CLK_LB 10 #define R8A7743_CLK_P 11 #define R8A7743_CLK_CL 12 #define R8A7743_CLK_M2 13 #define R8A7743_CLK_ZB3 15 #define R8A7743_CLK_ZB3D2 16 #define R8A7743_CLK_DDR 17 #define R8A7743_CLK_SDH 18 #define R8A7743_CLK_SD0 19 #define R8A7743_CLK_SD2 20 #define R8A7743_CLK_SD3 21 #define R8A7743_CLK_MMC0 22 #define R8A7743_CLK_MP 23 #define R8A7743_CLK_QSPI 26 #define R8A7743_CLK_CP 27 #define R8A7743_CLK_RCAN 28 #define R8A7743_CLK_R 29 #define R8A7743_CLK_OSC 30 #endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */ net-next plumbingsTobias Klauser
summaryrefslogtreecommitdiff
path: root/net/strparser/strparser.c
diff options
context:
space:
mode:
authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /net/strparser/strparser.c
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'net/strparser/strparser.c')