/* * Copyright (c) 2013 Heiko Stuebner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants clock controllers of Samsung S3C2410 and later. */ #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H /* * Let each exported clock get a unique index, which is used on DT-enabled * platforms to lookup the clock from a clock specifier. These indices are * therefore considered an ABI and so must not be changed. This implies * that new clocks should be added either in free spaces between clock groups * or at the end. */ /* Core clocks. */ /* id 1 is reserved */ #define MPLL 2 #define UPLL 3 #define FCLK 4 #define HCLK 5 #define PCLK 6 #define UCLK 7 #define ARMCLK 8 /* pclk-gates */ #define PCLK_UART0 16 #define PCLK_UART1 17 #define PCLK_UART2 18 #define PCLK_I2C 19 #define PCLK_SDI 20 #define PCLK_SPI 21 #define PCLK_ADC 22 #define PCLK_AC97 23 #define PCLK_I2S 24 #define PCLK_PWM 25 #define PCLK_RTC 26 #define PCLK_GPIO 27 /* hclk-gates */ #define HCLK_LCD 32 #define HCLK_USBH 33 #define HCLK_USBD 34 #define HCLK_NAND 35 #define HCLK_CAM 36 #define CAMIF 40 /* Total number of clocks. */ #define NR_CLKS (CAMIF + 1) #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ >Tobias Klauser
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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2017-01-29 15:07:34 +0300
committerDavid S. Miller <davem@davemloft.net>2017-01-30 22:05:43 -0500
commit1a0bee6c1e788218fd1d141db320db970aace7f0 (patch)
tree46c4116bc8ef4a7df718516a648597d9e21c15f1 /tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
parent63c190429020a9701b42887ac22c28f287f1762f (diff)
sh_eth: rename EESIPR bits
Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json')