/* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Mateusz Krawczuk * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants for Samsung S5PV210 clock controller. */ #ifndef _DT_BINDINGS_CLOCK_S5PV210_H #define _DT_BINDINGS_CLOCK_S5PV210_H /* Core clocks. */ #define FIN_PLL 1 #define FOUT_APLL 2 #define FOUT_MPLL 3 #define FOUT_EPLL 4 #define FOUT_VPLL 5 /* Muxes. */ #define MOUT_FLASH 6 #define MOUT_PSYS 7 #define MOUT_DSYS 8 #define MOUT_MSYS 9 #define MOUT_VPLL 10 #define MOUT_EPLL 11 #define MOUT_MPLL 12 #define MOUT_APLL 13 #define MOUT_VPLLSRC 14 #define MOUT_CSIS 15 #define MOUT_FIMD 16 #define MOUT_CAM1 17 #define MOUT_CAM0 18 #define MOUT_DAC 19 #define MOUT_MIXER 20 #define MOUT_HDMI 21 #define MOUT_G2D 22 #define MOUT_MFC 23 #define MOUT_G3D 24 #define MOUT_FIMC2 25 #define MOUT_FIMC1 26 #define MOUT_FIMC0 27 #define MOUT_UART3 28 #define MOUT_UART2 29 #define MOUT_UART1 30 #define MOUT_UART0 31 #define MOUT_MMC3 32 #define MOUT_MMC2 33 #define MOUT_MMC1 34 #define MOUT_MMC0 35 #define MOUT_PWM 36 #define MOUT_SPI0 37 #define MOUT_SPI1 38 #define MOUT_DMC0 39 #define MOUT_PWI 40 #define MOUT_HPM 41 #define MOUT_SPDIF 42 #define MOUT_AUDIO2 43 #define MOUT_AUDIO1 44 #define MOUT_AUDIO0 45 /* Dividers. */ #define DOUT_PCLKP 46 #define DOUT_HCLKP 47 #define DOUT_PCLKD 48 #define DOUT_HCLKD 49 #define DOUT_PCLKM 50 #define DOUT_HCLKM 51 #define DOUT_A2M 52 #define DOUT_APLL 53 #define DOUT_CSIS 54 #define DOUT_FIMD 55 #define DOUT_CAM1 56 #define DOUT_CAM0 57 #define DOUT_TBLK 58 #define DOUT_G2D 59 #define DOUT_MFC 60 #define DOUT_G3D 61 #define DOUT_FIMC2 62 #define DOUT_FIMC1 63 #define DOUT_FIMC0 64 #define DOUT_UART3 65 #define DOUT_UART2 66 #define DOUT_UART1 67 #define DOUT_UART0 68 #define DOUT_MMC3 69 #define DOUT_MMC2 70 #define DOUT_MMC1 71 #define DOUT_MMC0 72 #define DOUT_PWM 73 #define DOUT_SPI1 74 #define DOUT_SPI0 75 #define DOUT_DMC0 76 #define DOUT_PWI 77 #define DOUT_HPM 78 #define DOUT_COPY 79 #define DOUT_FLASH 80 #define DOUT_AUDIO2 81 #define DOUT_AUDIO1 82 #define DOUT_AUDIO0 83 #define DOUT_DPM 84 #define DOUT_DVSEM 85 /* Gates */ #define SCLK_FIMC 86 #define CLK_CSIS 87 #define CLK_ROTATOR 88 #define CLK_FIMC2 89 #define CLK_FIMC1 90 #define CLK_FIMC0 91 #define CLK_MFC 92 #define CLK_G2D 93 #define CLK_G3D 94 #define CLK_IMEM 95 #define CLK_PDMA1 96 #define CLK_PDMA0 97 #define CLK_MDMA 98 #define CLK_DMC1 99 #define CLK_DMC0 100 #define CLK_NFCON 101 #define CLK_SROMC 102 #define CLK_CFCON 103 #define CLK_NANDXL 104 #define CLK_USB_HOST 105 #define CLK_USB_OTG 106 #define CLK_HDMI 107 #define CLK_TVENC 108 #define CLK_MIXER 109 #define CLK_VP 110 #define CLK_DSIM 111 #define CLK_FIMD 112 #define CLK_TZIC3 113 #define CLK_TZIC2 114 #define CLK_TZIC1 115 #define CLK_TZIC0 116 #define CLK_VIC3 117 #define CLK_VIC2 118 #define CLK_VIC1 119 #define CLK_VIC0 120 #define CLK_TSI 121 #define CLK_HSMMC3 122 #define CLK_HSMMC2 123 #define CLK_HSMMC1 124 #define CLK_HSMMC0 125 #define CLK_JTAG 126 #define CLK_MODEMIF 127 #define CLK_CORESIGHT 128 #define CLK_SDM 129 #define CLK_SECSS 130 #define CLK_PCM2 131 #define CLK_PCM1 132 #define CLK_PCM0 133 #define CLK_SYSCON 134 #define CLK_GPIO 135 #define CLK_TSADC 136 #define CLK_PWM 137 #define CLK_WDT 138 #define CLK_KEYIF 139 #define CLK_UART3 140 #define CLK_UART2 141 #define CLK_UART1 142 #define CLK_UART0 143 #define CLK_SYSTIMER 144 #define CLK_RTC 145 #define CLK_SPI1 146 #define CLK_SPI0 147 #define CLK_I2C_HDMI_PHY 148 #define CLK_I2C1 149 #define CLK_I2C2 150 #define CLK_I2C0 151 #define CLK_I2S1 152 #define CLK_I2S2 153 #define CLK_I2S0 154 #define CLK_AC97 155 #define CLK_SPDIF 156 #define CLK_TZPC3 157 #define CLK_TZPC2 158 #define CLK_TZPC1 159 #define CLK_TZPC0 160 #define CLK_SECKEY 161 #define CLK_IEM_APC 162 #define CLK_IEM_IEC 163 #define CLK_CHIPID 164 #define CLK_JPEG 163 /* Special clocks*/ #define SCLK_PWI 164 #define SCLK_SPDIF 165 #define SCLK_AUDIO2 166 #define SCLK_AUDIO1 167 #define SCLK_AUDIO0 168 #define SCLK_PWM 169 #define SCLK_SPI1 170 #define SCLK_SPI0 171 #define SCLK_UART3 172 #define SCLK_UART2 173 #define SCLK_UART1 174 #define SCLK_UART0 175 #define SCLK_MMC3 176 #define SCLK_MMC2 177 #define SCLK_MMC1 178 #define SCLK_MMC0 179 #define SCLK_FINVPLL 180 #define SCLK_CSIS 181 #define SCLK_FIMD 182 #define SCLK_CAM1 183 #define SCLK_CAM0 184 #define SCLK_DAC 185 #define SCLK_MIXER 186 #define SCLK_HDMI 187 #define SCLK_FIMC2 188 #define SCLK_FIMC1 189 #define SCLK_FIMC0 190 #define SCLK_HDMI27M 191 #define SCLK_HDMIPHY 192 #define SCLK_USBPHY0 193 #define SCLK_USBPHY1 194 /* S5P6442-specific clocks */ #define MOUT_D0SYNC 195 #define MOUT_D1SYNC 196 #define DOUT_MIXER 197 #define CLK_ETB 198 #define CLK_ETM 199 /* CLKOUT */ #define FOUT_APLL_CLKOUT 200 #define FOUT_MPLL_CLKOUT 201 #define DOUT_APLL_CLKOUT 202 #define MOUT_CLKSEL 203 #define DOUT_CLKOUT 204 #define MOUT_CLKOUT 205 /* Total number of clocks. */ #define NR_CLKS 206 #endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ ?h=nds-private-remove&id=cadb9c9fdbc6a624d57b5ecdfd412b5800848703'>plain -rw-r--r--axis,artpec6-clkctrl.h1112logplain -rw-r--r--bcm-cygnus.h3135logplain -rw-r--r--bcm-ns2.h2915logplain -rw-r--r--bcm-nsp.h2148logplain -rw-r--r--bcm21664.h1984logplain -rw-r--r--bcm281xx.h2456logplain -rw-r--r--bcm2835-aux.h635logplain -rw-r--r--bcm2835.h1962logplain -rw-r--r--berlin2.h1034logplain -rw-r--r--berlin2q.h695logplain -rw-r--r--clps711x-clock.h718logplain -rw-r--r--efm32-cmu.h1112logplain -rw-r--r--exynos-audss-clk.h597logplain -rw-r--r--exynos3250.h9083logplain -rw-r--r--exynos4.h8284logplain -rw-r--r--exynos4415.h9828logplain -rw-r--r--exynos5250.h4616logplain -rw-r--r--exynos5260-clk.h14876logplain -rw-r--r--exynos5410.h1689logplain -rw-r--r--exynos5420.h6857logplain -rw-r--r--exynos5433.h45372logplain -rw-r--r--exynos5440.h1141logplain -rw-r--r--exynos7-clk.h5281logplain -rw-r--r--gxbb-aoclkc.h2866logplain -rw-r--r--gxbb-clkc.h592logplain -rw-r--r--hi3516cv300-clock.h1668logplain -rw-r--r--hi3519-clock.h1328logplain -rw-r--r--hi3620-clock.h4496logplain -rw-r--r--hi6220-clock.h4508logplain -rw-r--r--hip04-clock.h1137logplain -rw-r--r--histb-clock.h2012logplain -rw-r--r--hix5hd2-clock.h2415logplain -rw-r--r--imx1-clock.h1055logplain -rw-r--r--imx21-clock.h2461logplain -rw-r--r--imx27-clock.h3494logplain -rw-r--r--imx5-clock.h7212logplain -rw-r--r--imx6qdl-clock.h9593logplain -rw-r--r--imx6sl-clock.h5849logplain -rw-r--r--imx6sx-clock.h9099logplain -rw-r--r--imx6ul-clock.h8203logplain -rw-r--r--imx7d-clock.h15974logplain -rw-r--r--jz4740-cgu.h1028logplain -rw-r--r--jz4780-cgu.h2470logplain -rw-r--r--lpc18xx-ccu.h2134logplain -rw-r--r--lpc18xx-cgu.h1142logplain -rw-r--r--lpc32xx-clock.h1633logplain -rw-r--r--lsi,axm5516-clks.h974logplain -rw-r--r--marvell,mmp2.h2022logplain -rw-r--r--marvell,pxa168.h1654logplain -rw-r--r--marvell,pxa1928.h1535logplain -rw-r--r--marvell,pxa910.h1598logplain -rw-r--r--maxim,max77620.h632logplain -rw-r--r--maxim,max77686.h648logplain -rw-r--r--maxim,max77802.h630logplain -rw-r--r--meson8b-clkc.h523logplain -rw-r--r--microchip,pic32-clock.h1150logplain -rw-r--r--mpc512x-clock.h2236logplain -rw-r--r--mt2701-clk.h13832logplain -rw-r--r--mt8135-clk.h5641logplain -rw-r--r--mt8173-clk.h9293logplain -rw-r--r--oxsemi,ox810se.h1002logplain -rw-r--r--oxsemi,ox820.h1203logplain -rw-r--r--pistachio-clk.h4863logplain -rw-r--r--pxa-clock.h1715logplain -rw-r--r--qcom,gcc-apq8084.h12872logplain -rw-r--r--qcom,gcc-ipq4019.h5423logplain -rw-r--r--qcom,gcc-ipq806x.h8574logplain -rw-r--r--qcom,gcc-mdm9615.h9497logplain -rw-r--r--qcom,gcc-msm8660.h7932logplain -rw-r--r--qcom,gcc-msm8916.h6190logplain -rw-r--r--qcom,gcc-msm8960.h9342logplain -rw-r--r--qcom,gcc-msm8974.h12340logplain -rw-r--r--qcom,gcc-msm8994.h4858logplain -rw-r--r--qcom,gcc-msm8996.h12575logplain -rw-r--r--qcom,lcc-ipq806x.h899logplain -rw-r--r--qcom,lcc-mdm9615.h1701logplain -rw-r--r--qcom,lcc-msm8960.h1616logplain -rw-r--r--qcom,mmcc-apq8084.h5722logplain -rw-r--r--qcom,mmcc-msm8960.h4109logplain -rw-r--r--qcom,mmcc-msm8974.h5223logplain -rw-r--r--qcom,mmcc-msm8996.h9403logplain -rw-r--r--qcom,rpmcc.h2101logplain -rw-r--r--r7s72100-clock.h1218logplain -rw-r--r--r8a73a4-clock.h1596logplain -rw-r--r--r8a7740-clock.h1992logplain -rw-r--r--r8a7743-cpg-mssr.h1269logplain -rw-r--r--r8a7745-cpg-mssr.h1298logplain -rw-r--r--r8a7778-clock.h1855logplain -rw-r--r--r8a7779-clock.h1647logplain -rw-r--r--r8a7790-clock.h4367logplain -rw-r--r--r8a7791-clock.h4388logplain -rw-r--r--r8a7792-clock.h2562logplain -rw-r--r--r8a7793-clock.h4561logplain -rw-r--r--r8a7794-clock.h3679logplain -rw-r--r--r8a7795-cpg-mssr.h1890logplain -rw-r--r--r8a7796-cpg-mssr.h2066logplain -rw-r--r--renesas-cpg-mssr.h542logplain -rw-r--r--rk1108-cru.h6605logplain -rw-r--r--rk3036-cru.h4584logplain -rw-r--r--rk3066a-cru.h1068logplain -rw-r--r--rk3188-cru-common.h6105logplain -rw-r--r--rk3188-cru.h1435logplain