/* * This header provides constants clk index STMicroelectronics * STiH410 SoC. */ #ifndef _DT_BINDINGS_CLK_STIH410 #define _DT_BINDINGS_CLK_STIH410 #include "stih407-clks.h" /* STiH410 introduces new clock outputs compared to STiH407 */ /* CLOCKGEN C0 */ #define CLK_TX_ICN_HADES 32 #define CLK_RX_ICN_HADES 33 #define CLK_ICN_REG_16 34 #define CLK_PP_HADES 35 #define CLK_CLUST_HADES 36 #define CLK_HWPE_HADES 37 #define CLK_FC_HADES 38 /* CLOCKGEN D0 */ #define CLK_PCMR10_MASTER 4 #define CLK_USB2_PHY 5 #endif nk rel='vcs-git' href='http:///git.distanz.ch/cgit.cgi/linux/net-next.git' title='net-next.git Git repository'/>
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authorJerome Brunet <jbrunet@baylibre.com>2017-01-20 08:20:24 -0800
committerArnd Bergmann <arnd@arndb.de>2017-01-27 16:46:42 +0100
commitfeb3cbea0946c67060e2d5bcb7499b0a6f6700fe (patch)
tree4789978854a7fd97de08f4b77f220bcd9278417b /include/uapi/video/edid.h
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage
OdroidC2 GbE link breaks under heavy tx transfer. This happens even if the MAC does not enable Energy Efficient Ethernet (No Low Power state Idle on the Tx path). The problem seems to come from the phy Rx path, entering the LPI state. Disabling EEE advertisement on the phy prevent this feature to be negociated with the link partner and solve the issue. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/uapi/video/edid.h')