/* * This header provides constants for binding nvidia,tegra186-gpio*. * * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below * provide names for this. * * The second cell contains standard flag values specified in gpio.h. */ #ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H #define _DT_BINDINGS_GPIO_TEGRA_GPIO_H #include /* GPIOs implemented by main GPIO controller */ #define TEGRA_MAIN_GPIO_PORT_A 0 #define TEGRA_MAIN_GPIO_PORT_B 1 #define TEGRA_MAIN_GPIO_PORT_C 2 #define TEGRA_MAIN_GPIO_PORT_D 3 #define TEGRA_MAIN_GPIO_PORT_E 4 #define TEGRA_MAIN_GPIO_PORT_F 5 #define TEGRA_MAIN_GPIO_PORT_G 6 #define TEGRA_MAIN_GPIO_PORT_H 7 #define TEGRA_MAIN_GPIO_PORT_I 8 #define TEGRA_MAIN_GPIO_PORT_J 9 #define TEGRA_MAIN_GPIO_PORT_K 10 #define TEGRA_MAIN_GPIO_PORT_L 11 #define TEGRA_MAIN_GPIO_PORT_M 12 #define TEGRA_MAIN_GPIO_PORT_N 13 #define TEGRA_MAIN_GPIO_PORT_O 14 #define TEGRA_MAIN_GPIO_PORT_P 15 #define TEGRA_MAIN_GPIO_PORT_Q 16 #define TEGRA_MAIN_GPIO_PORT_R 17 #define TEGRA_MAIN_GPIO_PORT_T 18 #define TEGRA_MAIN_GPIO_PORT_X 19 #define TEGRA_MAIN_GPIO_PORT_Y 20 #define TEGRA_MAIN_GPIO_PORT_BB 21 #define TEGRA_MAIN_GPIO_PORT_CC 22 #define TEGRA_MAIN_GPIO(port, offset) \ ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset) /* GPIOs implemented by AON GPIO controller */ #define TEGRA_AON_GPIO_PORT_S 0 #define TEGRA_AON_GPIO_PORT_U 1 #define TEGRA_AON_GPIO_PORT_V 2 #define TEGRA_AON_GPIO_PORT_W 3 #define TEGRA_AON_GPIO_PORT_Z 4 #define TEGRA_AON_GPIO_PORT_AA 5 #define TEGRA_AON_GPIO_PORT_EE 6 #define TEGRA_AON_GPIO_PORT_FF 7 #define TEGRA_AON_GPIO(port, offset) \ ((TEGRA_AON_GPIO_PORT_##port * 8) + offset) #endif /refs/?h=nds-private-remove&id=dfef358bd1beb4e7b5c94eca944be9cd23dfc752'>refslogtreecommitdiff
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authorChristoph Hellwig <hch@lst.de>2017-01-30 13:15:41 +0100
committerBjorn Helgaas <bhelgaas@google.com>2017-02-02 10:35:46 -0600
commitdfef358bd1beb4e7b5c94eca944be9cd23dfc752 (patch)
treeb9a2afb38a4c2ac8ad31f49ec0d71fe9e5b1994c /net/irda/irias_object.c
parent030305d69fc6963c16003f50d7e8d74b02d0a143 (diff)
PCI/MSI: Don't apply affinity if there aren't enough vectors left
Bart reported a problem wіth an out of bounds access in the low-level IRQ affinity code, which we root caused to the qla2xxx driver assigning all its MSI-X vectors to the pre and post vectors, and not having any left for the actually spread IRQs. Fix this issue by not asking for affinity assignment when there are no vectors to assign left. Fixes: 402723ad5c62 ("PCI/MSI: Provide pci_alloc_irq_vectors_affinity()") Link: https://lkml.kernel.org/r/1485359225.3093.3.camel@sandisk.com Reported-by: Bart Van Assche <bart.vanassche@sandisk.com> Tested-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'net/irda/irias_object.c')