/* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf #endif > summaryrefslogtreecommitdiff
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authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /tools/perf/util/data.h
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'tools/perf/util/data.h')