/* * This header provides constants specific to AM43XX pinctrl bindings. */ #ifndef _DT_BINDINGS_PINCTRL_AM43XX_H #define _DT_BINDINGS_PINCTRL_AM43XX_H #define MUX_MODE0 0 #define MUX_MODE1 1 #define MUX_MODE2 2 #define MUX_MODE3 3 #define MUX_MODE4 4 #define MUX_MODE5 5 #define MUX_MODE6 6 #define MUX_MODE7 7 #define MUX_MODE8 8 #define MUX_MODE9 9 #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) #define SLEWCTRL_SLOW (1 << 19) #define SLEWCTRL_FAST 0 #define DS0_PULL_UP_DOWN_EN (1 << 27) #define WAKEUP_ENABLE (1 << 29) #define PIN_OUTPUT (PULL_DISABLE) #define PIN_OUTPUT_PULLUP (PULL_UP) #define PIN_OUTPUT_PULLDOWN 0 #define PIN_INPUT (INPUT_EN | PULL_DISABLE) #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) /* * Macro to allow using the absolute physical address instead of the * padconf registers instead of the offset from padconf base. */ #define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) #endif b72b94'/> net-next plumbingsTobias Klauser
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authorGiovanni Cabiddu <giovanni.cabiddu@intel.com>2016-12-22 15:00:12 +0000
committerHerbert Xu <herbert@gondor.apana.org.au>2017-02-02 21:54:52 +0800
commit3484ecbe0e9deb94afb0b9b6172d77e98eb72b94 (patch)
tree4d4be0d20d4946c51ef47a882d78c9934a219c0e /tools/perf/Documentation/perf-inject.txt
parent11e3b725cfc282efe9d4a354153e99d86a16af08 (diff)
crypto: qat - fix bar discovery for c62x
Some accelerators of the c62x series have only two bars. This patch skips BAR0 if the accelerator does not have it. Cc: <stable@vger.kernel.org> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'tools/perf/Documentation/perf-inject.txt')