/* * This header provides constants specific to AM43XX pinctrl bindings. */ #ifndef _DT_BINDINGS_PINCTRL_AM43XX_H #define _DT_BINDINGS_PINCTRL_AM43XX_H #define MUX_MODE0 0 #define MUX_MODE1 1 #define MUX_MODE2 2 #define MUX_MODE3 3 #define MUX_MODE4 4 #define MUX_MODE5 5 #define MUX_MODE6 6 #define MUX_MODE7 7 #define MUX_MODE8 8 #define MUX_MODE9 9 #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) #define SLEWCTRL_SLOW (1 << 19) #define SLEWCTRL_FAST 0 #define DS0_PULL_UP_DOWN_EN (1 << 27) #define WAKEUP_ENABLE (1 << 29) #define PIN_OUTPUT (PULL_DISABLE) #define PIN_OUTPUT_PULLUP (PULL_UP) #define PIN_OUTPUT_PULLDOWN 0 #define PIN_INPUT (INPUT_EN | PULL_DISABLE) #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) /* * Macro to allow using the absolute physical address instead of the * padconf registers instead of the offset from padconf base. */ #define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) #endif 90d3dd1'/> net-next plumbingsTobias Klauser
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authorAlexander Stein <alexander.stein@systec-electronic.com>2017-01-30 12:35:28 +0100
committerLinus Walleij <linus.walleij@linaro.org>2017-01-30 15:53:57 +0100
commitcdca06e4e85974d8a3503ab15709dbbaf90d3dd1 (patch)
tree268b0c01070a957006db97c88dccb5fb061440ff /net/mac80211/ieee80211_i.h
parent1b89970d81bbd52720fc64a3fe9572ee33588363 (diff)
pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler
According to VLI64 Intel Atom E3800 Specification Update (#329901) concurrent read accesses may result in returning 0xffffffff and write accesses may be dropped silently. To workaround all accesses must be protected by locks. Cc: stable@vger.kernel.org Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'net/mac80211/ieee80211_i.h')