/*
* Copyright (C) 2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7795_PD_CA57_CPU0 0
#define R8A7795_PD_CA57_CPU1 1
#define R8A7795_PD_CA57_CPU2 2
#define R8A7795_PD_CA57_CPU3 3
#define R8A7795_PD_CA53_CPU0 5
#define R8A7795_PD_CA53_CPU1 6
#define R8A7795_PD_CA53_CPU2 7
#define R8A7795_PD_CA53_CPU3 8
#define R8A7795_PD_A3VP 9
#define R8A7795_PD_CA57_SCU 12
#define R8A7795_PD_CR7 13
#define R8A7795_PD_A3VC 14
#define R8A7795_PD_3DG_A 17
#define R8A7795_PD_3DG_B 18
#define R8A7795_PD_3DG_C 19
#define R8A7795_PD_3DG_D 20
#define R8A7795_PD_CA53_SCU 21
#define R8A7795_PD_3DG_E 22
#define R8A7795_PD_A3IR 24
#define R8A7795_PD_A2VC0 25
#define R8A7795_PD_A2VC1 26
/* Always-on power area */
#define R8A7795_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
pump-back'>packet-rx-pump-back
stmmac: Discard masked flags in interrupt status register
DW GMAC databook says the following about bits in "Register 15 (Interrupt
Mask Register)":
--------------------------->8-------------------------
When set, this bit __disables_the_assertion_of_the_interrupt_signal__
because of the setting of XXX bit in Register 14 (Interrupt
Status Register).
--------------------------->8-------------------------
In fact even if we mask one bit in the mask register it doesn't prevent
corresponding bit to appear in the status register, it only disables
interrupt generation for corresponding event.
But currently we expect a bit different behavior: status bits to be in
sync with their masks, i.e. if mask for bit A is set in the mask
register then bit A won't appear in the interrupt status register.
This was proven to be incorrect assumption, see discussion here [1].
That misunderstanding causes unexpected behaviour of the GMAC, for
example we were happy enough to just see bogus messages about link
state changes.
So from now on we'll be only checking bits that really may trigger an
interrupt.
[1] https://lkml.org/lkml/2016/11/3/413
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Fabrice Gasnier <fabrice.gasnier@st.com>
Cc: Joachim Eastwood <manabian@gmail.com>
Cc: Phil Reid <preid@electromag.com.au>
Cc: David Miller <davem@davemloft.net>
Cc: Alexandre Torgue <alexandre.torgue@gmail.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>