/* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * GPL LICENSE SUMMARY * * Copyright (c) 2016 BayLibre, SAS. * Author: Neil Armstrong * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see . * The full GNU General Public License is included in this distribution * in the file called COPYING. * * BSD LICENSE * * Copyright (c) 2016 BayLibre, SAS. * Author: Neil Armstrong * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H /* RESET0 */ #define RESET_HIU 0 /* 1 */ #define RESET_DOS_RESET 2 #define RESET_DDR_TOP 3 #define RESET_DCU_RESET 4 #define RESET_VIU 5 #define RESET_AIU 6 #define RESET_VID_PLL_DIV 7 /* 8 */ #define RESET_PMUX 9 #define RESET_VENC 10 #define RESET_ASSIST 11 #define RESET_AFIFO2 12 #define RESET_VCBUS 13 /* 14 */ /* 15 */ #define RESET_GIC 16 #define RESET_CAPB3_DECODE 17 #define RESET_NAND_CAPB3 18 #define RESET_HDMITX_CAPB3 19 #define RESET_MALI_CAPB3 20 #define RESET_DOS_CAPB3 21 #define RESET_SYS_CPU_CAPB3 22 #define RESET_CBUS_CAPB3 23 #define RESET_AHB_CNTL 24 #define RESET_AHB_DATA 25 #define RESET_VCBUS_CLK81 26 #define RESET_MMC 27 #define RESET_MIPI_0 28 #define RESET_MIPI_1 29 #define RESET_MIPI_2 30 #define RESET_MIPI_3 31 /* RESET1 */ #define RESET_CPPM 32 #define RESET_DEMUX 33 #define RESET_USB_OTG 34 #define RESET_DDR 35 #define RESET_AO_RESET 36 #define RESET_BT656 37 #define RESET_AHB_SRAM 38 /* 39 */ #define RESET_PARSER 40 #define RESET_BLKMV 41 #define RESET_ISA 42 #define RESET_ETHERNET 43 #define RESET_SD_EMMC_A 44 #define RESET_SD_EMMC_B 45 #define RESET_SD_EMMC_C 46 #define RESET_ROM_BOOT 47 #define RESET_SYS_CPU_0 48 #define RESET_SYS_CPU_1 49 #define RESET_SYS_CPU_2 50 #define RESET_SYS_CPU_3 51 #define RESET_SYS_CPU_CORE_0 52 #define RESET_SYS_CPU_CORE_1 53 #define RESET_SYS_CPU_CORE_2 54 #define RESET_SYS_CPU_CORE_3 55 #define RESET_SYS_PLL_DIV 56 #define RESET_SYS_CPU_AXI 57 #define RESET_SYS_CPU_L2 58 #define RESET_SYS_CPU_P 59 #define RESET_SYS_CPU_MBIST 60 /* 61 */ /* 62 */ /* 63 */ /* RESET2 */ #define RESET_VD_RMEM 64 #define RESET_AUDIN 65 #define RESET_HDMI_TX 66 /* 67 */ /* 68 */ /* 69 */ #define RESET_GE2D 70 #define RESET_PARSER_REG 71 #define RESET_PARSER_FETCH 72 #define RESET_PARSER_CTL 73 #define RESET_PARSER_TOP 74 /* 75 */ /* 76 */ #define RESET_AO_CPU_RESET 77 #define RESET_MALI 78 #define RESET_HDMI_SYSTEM_RESET 79 /* 80-95 */ /* RESET3 */ #define RESET_RING_OSCILLATOR 96 #define RESET_SYS_CPU 97 #define RESET_EFUSE 98 #define RESET_SYS_CPU_BVCI 99 #define RESET_AIFIFO 100 #define RESET_TVFE 101 #define RESET_AHB_BRIDGE_CNTL 102 /* 103 */ #define RESET_AUDIO_DAC 104 #define RESET_DEMUX_TOP 105 #define RESET_DEMUX_DES 106 #define RESET_DEMUX_S2P_0 107 #define RESET_DEMUX_S2P_1 108 #define RESET_DEMUX_RESET_0 109 #define RESET_DEMUX_RESET_1 110 #define RESET_DEMUX_RESET_2 111 /* 112-127 */ /* RESET4 */ /* 128 */ /* 129 */ /* 130 */ /* 131 */ #define RESET_DVIN_RESET 132 #define RESET_RDMA 133 #define RESET_VENCI 134 #define RESET_VENCP 135 /* 136 */ #define RESET_VDAC 137 #define RESET_RTC 138 /* 139 */ #define RESET_VDI6 140 #define RESET_VENCL 141 #define RESET_I2C_MASTER_2 142 #define RESET_I2C_MASTER_1 143 /* 144-159 */ /* RESET5 */ /* 160-191 */ /* RESET6 */ #define RESET_PERIPHS_GENERAL 192 #define RESET_PERIPHS_SPICC 193 #define RESET_PERIPHS_SMART_CARD 194 #define RESET_PERIPHS_SAR_ADC 195 #define RESET_PERIPHS_I2C_MASTER_0 196 #define RESET_SANA 197 /* 198 */ #define RESET_PERIPHS_STREAM_INTERFACE 199 #define RESET_PERIPHS_SDIO 200 #define RESET_PERIPHS_UART_0 201 #define RESET_PERIPHS_UART_1_2 202 #define RESET_PERIPHS_ASYNC_0 203 #define RESET_PERIPHS_ASYNC_1 204 #define RESET_PERIPHS_SPI_0 205 #define RESET_PERIPHS_SDHC 206 #define RESET_UART_SLIP 207 /* 208-223 */ /* RESET7 */ #define RESET_USB_DDR_0 224 #define RESET_USB_DDR_1 225 #define RESET_USB_DDR_2 226 #define RESET_USB_DDR_3 227 /* 228 */ #define RESET_DEVICE_MMC_ARB 229 /* 230 */ #define RESET_VID_LOCK 231 #define RESET_A9_DMC_PIPEL 232 /* 233-255 */ #endif when the code was introduced, but only in the corner case when an event is allocated, but more crtc's were included by atomic check and then failing. This can mostly happen when you do an atomic modeset in i915 and the display clock is changed, which forces all crtc's to be included to the state. This has been broken worse by adding in-fences support, which caused the double free to be done unconditionally. [IGT] kms_rotation_crc: starting subtest primary-rotation-180 ============================================================================= BUG kmalloc-128 (Tainted: G U ): Object already free ----------------------------------------------------------------------------- Disabling lock debugging due to kernel taint INFO: Allocated in drm_atomic_helper_setup_commit+0x285/0x2f0 [drm_kms_helper] age=0 cpu=3 pid=1529 ___slab_alloc+0x308/0x3b0 __slab_alloc+0xd/0x20 kmem_cache_alloc_trace+0x92/0x1c0 drm_atomic_helper_setup_commit+0x285/0x2f0 [drm_kms_helper] intel_atomic_commit+0x35/0x4f0 [i915] drm_atomic_commit+0x46/0x50 [drm] drm_mode_atomic_ioctl+0x7d4/0xab0 [drm] drm_ioctl+0x2b3/0x490 [drm] do_vfs_ioctl+0x69c/0x700 SyS_ioctl+0x4e/0x80 entry_SYSCALL_64_fastpath+0x13/0x94 INFO: Freed in drm_event_cancel_free+0xa3/0xb0 [drm] age=0 cpu=3 pid=1529 __slab_free+0x48/0x2e0 kfree+0x159/0x1a0 drm_event_cancel_free+0xa3/0xb0 [drm] drm_mode_atomic_ioctl+0x86d/0xab0 [drm] drm_ioctl+0x2b3/0x490 [drm] do_vfs_ioctl+0x69c/0x700 SyS_ioctl+0x4e/0x80 entry_SYSCALL_64_fastpath+0x13/0x94 INFO: Slab 0xffffde1f0997b080 objects=17 used=2 fp=0xffff92fb65ec2578 flags=0x200000000008101 INFO: Object 0xffff92fb65ec2578 @offset=1400 fp=0xffff92fb65ec2ae8 Redzone ffff92fb65ec2570: bb bb bb bb bb bb bb bb ........ Object ffff92fb65ec2578: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec2588: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec2598: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25a8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25b8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25c8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25d8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25e8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 kkkkkkkkkkkkkkk. Redzone ffff92fb65ec25f8: bb bb bb bb bb bb bb bb ........ Padding ffff92fb65ec2738: 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ CPU: 3 PID: 180 Comm: kworker/3:2 Tainted: G BU 4.10.0-rc6-patser+ #5039 Hardware name: /NUC5PPYB, BIOS PYBSWCEL.86A.0031.2015.0601.1712 06/01/2015 Workqueue: events intel_atomic_helper_free_state [i915] Call Trace: dump_stack+0x4d/0x6d print_trailer+0x20c/0x220 free_debug_processing+0x1c6/0x330 ? drm_atomic_state_default_clear+0xf7/0x1c0 [drm] __slab_free+0x48/0x2e0 ? drm_atomic_state_default_clear+0xf7/0x1c0 [drm] kfree+0x159/0x1a0 drm_atomic_state_default_clear+0xf7/0x1c0 [drm] ? drm_atomic_state_clear+0x30/0x30 [drm] intel_atomic_state_clear+0xd/0x20 [i915] drm_atomic_state_clear+0x1a/0x30 [drm] __drm_atomic_state_free+0x13/0x60 [drm] intel_atomic_helper_free_state+0x5d/0x70 [i915] process_one_work+0x260/0x4a0 worker_thread+0x2d1/0x4f0 kthread+0x127/0x130 ? process_one_work+0x4a0/0x4a0 ? kthread_stop+0x120/0x120 ret_from_fork+0x29/0x40 FIX kmalloc-128: Object at 0xffff92fb65ec2578 not freed Fixes: 3b24f7d67581 ("drm/atomic: Add struct drm_crtc_commit to track async updates") Fixes: 9626014258a5 ("drm/fence: add in-fences support") Cc: <stable@vger.kernel.org> # v4.8+ Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1485854725-27640-1-git-send-email-maarten.lankhorst@linux.intel.com
Diffstat (limited to 'include/trace/events/huge_memory.h')