/** * This header provides index for the reset controller * based on hi6220 SoC. */ #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 #define PERIPH_RSTDIS0_MMC0 0x000 #define PERIPH_RSTDIS0_MMC1 0x001 #define PERIPH_RSTDIS0_MMC2 0x002 #define PERIPH_RSTDIS0_NANDC 0x003 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 #define PERIPH_RSTDIS0_USBOTG 0x006 #define PERIPH_RSTDIS0_USBOTG_32K 0x007 #define PERIPH_RSTDIS1_HIFI 0x100 #define PERIPH_RSTDIS1_DIGACODEC 0x105 #define PERIPH_RSTEN2_IPF 0x200 #define PERIPH_RSTEN2_SOCP 0x201 #define PERIPH_RSTEN2_DMAC 0x202 #define PERIPH_RSTEN2_SECENG 0x203 #define PERIPH_RSTEN2_ABB 0x204 #define PERIPH_RSTEN2_HPM0 0x205 #define PERIPH_RSTEN2_HPM1 0x206 #define PERIPH_RSTEN2_HPM2 0x207 #define PERIPH_RSTEN2_HPM3 0x208 #define PERIPH_RSTEN3_CSSYS 0x300 #define PERIPH_RSTEN3_I2C0 0x301 #define PERIPH_RSTEN3_I2C1 0x302 #define PERIPH_RSTEN3_I2C2 0x303 #define PERIPH_RSTEN3_I2C3 0x304 #define PERIPH_RSTEN3_UART1 0x305 #define PERIPH_RSTEN3_UART2 0x306 #define PERIPH_RSTEN3_UART3 0x307 #define PERIPH_RSTEN3_UART4 0x308 #define PERIPH_RSTEN3_SSP 0x309 #define PERIPH_RSTEN3_PWM 0x30a #define PERIPH_RSTEN3_BLPWM 0x30b #define PERIPH_RSTEN3_TSENSOR 0x30c #define PERIPH_RSTEN3_DAPB 0x312 #define PERIPH_RSTEN3_HKADC 0x313 #define PERIPH_RSTEN3_CODEC_SSI 0x314 #define PERIPH_RSTEN3_PMUSSI1 0x316 #define PERIPH_RSTEN8_RS0 0x400 #define PERIPH_RSTEN8_RS2 0x401 #define PERIPH_RSTEN8_RS3 0x402 #define PERIPH_RSTEN8_MS0 0x403 #define PERIPH_RSTEN8_MS2 0x405 #define PERIPH_RSTEN8_XG2RAM0 0x406 #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 #define PERIPH_RSTEN8_SRAM 0x408 #define PERIPH_RSTEN8_HARQ 0x40a #define PERIPH_RSTEN8_DDRC 0x40c #define PERIPH_RSTEN8_DDRC_APB 0x40d #define PERIPH_RSTEN8_DDRPACK_APB 0x40e #define PERIPH_RSTEN8_DDRT 0x411 #define PERIPH_RSDIST9_CARM_DAP 0x500 #define PERIPH_RSDIST9_CARM_ATB 0x501 #define PERIPH_RSDIST9_CARM_LBUS 0x502 #define PERIPH_RSDIST9_CARM_POR 0x503 #define PERIPH_RSDIST9_CARM_CORE 0x504 #define PERIPH_RSDIST9_CARM_DBG 0x505 #define PERIPH_RSDIST9_CARM_L2 0x506 #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 #define PERIPH_RSDIST9_CARM_ETM 0x508 #define MEDIA_G3D 0 #define MEDIA_CODEC_VPU 2 #define MEDIA_CODEC_JPEG 3 #define MEDIA_ISP 4 #define MEDIA_ADE 5 #define MEDIA_MMU 6 #define MEDIA_XG2RAM1 7 #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ de/uapi/drm/exynos_drm.h?id=040587af31228d82c52267f717c9fcdb65f36335'>exynos_drm.h
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authorSimon Horman <simon.horman@netronome.com>2017-01-30 16:19:02 +0100
committerDavid S. Miller <davem@davemloft.net>2017-01-30 16:42:09 -0500
commit040587af31228d82c52267f717c9fcdb65f36335 (patch)
treeb681c1594f967396fcf3ce80f17444183bb37900 /include/uapi/drm/exynos_drm.h
parent0d29ed28da63dd893395c343c7e78b078de93ceb (diff)
net/sched: cls_flower: Correct matching on ICMPv6 code
When matching on the ICMPv6 code ICMPV6_CODE rather than ICMPV4_CODE attributes should be used. This corrects what appears to be a typo. Sample usage: tc qdisc add dev eth0 ingress tc filter add dev eth0 protocol ipv6 parent ffff: flower \ indev eth0 ip_proto icmpv6 type 128 code 0 action drop Without this change the code parameter above is effectively ignored. Fixes: 7b684884fbfa ("net/sched: cls_flower: Support matching on ICMP type and code") Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/uapi/drm/exynos_drm.h')