/* * Copyright (c) 2015 MediaTek, Shunli Wang * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 #define _DT_BINDINGS_RESET_CONTROLLER_MT2701 /* INFRACFG resets */ #define MT2701_INFRA_EMI_REG_RST 0 #define MT2701_INFRA_DRAMC0_A0_RST 1 #define MT2701_INFRA_FHCTL_RST 2 #define MT2701_INFRA_APCIRQ_EINT_RST 3 #define MT2701_INFRA_APXGPT_RST 4 #define MT2701_INFRA_SCPSYS_RST 5 #define MT2701_INFRA_KP_RST 6 #define MT2701_INFRA_PMIC_WRAP_RST 7 #define MT2701_INFRA_MIPI_RST 8 #define MT2701_INFRA_IRRX_RST 9 #define MT2701_INFRA_CEC_RST 10 #define MT2701_INFRA_EMI_RST 32 #define MT2701_INFRA_DRAMC0_RST 34 #define MT2701_INFRA_TRNG_RST 37 #define MT2701_INFRA_SYSIRQ_RST 38 /* PERICFG resets */ #define MT2701_PERI_UART0_SW_RST 0 #define MT2701_PERI_UART1_SW_RST 1 #define MT2701_PERI_UART2_SW_RST 2 #define MT2701_PERI_UART3_SW_RST 3 #define MT2701_PERI_GCPU_SW_RST 5 #define MT2701_PERI_BTIF_SW_RST 6 #define MT2701_PERI_PWM_SW_RST 8 #define MT2701_PERI_AUXADC_SW_RST 10 #define MT2701_PERI_DMA_SW_RST 11 #define MT2701_PERI_NFI_SW_RST 14 #define MT2701_PERI_NLI_SW_RST 15 #define MT2701_PERI_THERM_SW_RST 16 #define MT2701_PERI_MSDC2_SW_RST 17 #define MT2701_PERI_MSDC0_SW_RST 19 #define MT2701_PERI_MSDC1_SW_RST 20 #define MT2701_PERI_I2C0_SW_RST 22 #define MT2701_PERI_I2C1_SW_RST 23 #define MT2701_PERI_I2C2_SW_RST 24 #define MT2701_PERI_I2C3_SW_RST 25 #define MT2701_PERI_USB_SW_RST 28 #define MT2701_PERI_ETH_SW_RST 29 #define MT2701_PERI_SPI0_SW_RST 33 /* TOPRGU resets */ #define MT2701_TOPRGU_INFRA_RST 0 #define MT2701_TOPRGU_MM_RST 1 #define MT2701_TOPRGU_MFG_RST 2 #define MT2701_TOPRGU_ETHDMA_RST 3 #define MT2701_TOPRGU_VDEC_RST 4 #define MT2701_TOPRGU_VENC_IMG_RST 5 #define MT2701_TOPRGU_DDRPHY_RST 6 #define MT2701_TOPRGU_MD_RST 7 #define MT2701_TOPRGU_INFRA_AO_RST 8 #define MT2701_TOPRGU_CONN_RST 9 #define MT2701_TOPRGU_APMIXED_RST 10 #define MT2701_TOPRGU_HIFSYS_RST 11 #define MT2701_TOPRGU_CONN_MCU_RST 12 #define MT2701_TOPRGU_BDP_DISP_RST 13 /* HIFSYS resets */ #define MT2701_HIFSYS_UHOST0_RST 3 #define MT2701_HIFSYS_UHOST1_RST 4 #define MT2701_HIFSYS_UPHY0_RST 21 #define MT2701_HIFSYS_UPHY1_RST 22 #define MT2701_HIFSYS_PCIE0_RST 24 #define MT2701_HIFSYS_PCIE1_RST 25 #define MT2701_HIFSYS_PCIE2_RST 26 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ ef='/cgit.cgi/linux/net-next.git/commit/net/ieee802154?id=91539eb1fda2d530d3b268eef542c5414e54bf1a'>ieee802154/6lowpan
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authorIago Abal <mail@iagoabal.eu>2017-01-11 14:00:21 +0100
committerVinod Koul <vinod.koul@intel.com>2017-01-25 15:35:11 +0530
commit91539eb1fda2d530d3b268eef542c5414e54bf1a (patch)
tree960f5ca6342ad20837aff18aad6e8ecd7da32fd6 /net/ieee802154/6lowpan
parent6610d0edf6dc7ee97e46ab3a538a565c79d26199 (diff)
dmaengine: pl330: fix double lock
The static bug finder EBA (http://www.iagoabal.eu/eba/) reported the following double-lock bug: Double lock: 1. spin_lock_irqsave(pch->lock, flags) at pl330_free_chan_resources:2236; 2. call to function `pl330_release_channel' immediately after; 3. call to function `dma_pl330_rqcb' in line 1753; 4. spin_lock_irqsave(pch->lock, flags) at dma_pl330_rqcb:1505. I have fixed it as suggested by Marek Szyprowski. First, I have replaced `pch->lock' with `pl330->lock' in functions `pl330_alloc_chan_resources' and `pl330_free_chan_resources'. This avoids the double-lock by acquiring a different lock than `dma_pl330_rqcb'. NOTE that, as a result, `pl330_free_chan_resources' executes `list_splice_tail_init' on `pch->work_list' under lock `pl330->lock', whereas in the rest of the code `pch->work_list' is protected by `pch->lock'. I don't know if this may cause race conditions. Similarly `pch->cyclic' is written by `pl330_alloc_chan_resources' under `pl330->lock' but read by `pl330_tx_submit' under `pch->lock'. Second, I have removed locking from `pl330_request_channel' and `pl330_release_channel' functions. Function `pl330_request_channel' is only called from `pl330_alloc_chan_resources', so the lock is already held. Function `pl330_release_channel' is called from `pl330_free_chan_resources', which already holds the lock, and from `pl330_del'. Function `pl330_del' is called in an error path of `pl330_probe' and at the end of `pl330_remove', but I assume that there cannot be concurrent accesses to the protected data at those points. Signed-off-by: Iago Abal <mail@iagoabal.eu> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'net/ieee802154/6lowpan')