/* * Copyright (c) 2013, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H #define _DT_BINDINGS_RESET_MSM_GCC_8974_H #define GCC_SYSTEM_NOC_BCR 0 #define GCC_CONFIG_NOC_BCR 1 #define GCC_PERIPH_NOC_BCR 2 #define GCC_IMEM_BCR 3 #define GCC_MMSS_BCR 4 #define GCC_QDSS_BCR 5 #define GCC_USB_30_BCR 6 #define GCC_USB3_PHY_BCR 7 #define GCC_USB_HS_HSIC_BCR 8 #define GCC_USB_HS_BCR 9 #define GCC_USB2A_PHY_BCR 10 #define GCC_USB2B_PHY_BCR 11 #define GCC_SDCC1_BCR 12 #define GCC_SDCC2_BCR 13 #define GCC_SDCC3_BCR 14 #define GCC_SDCC4_BCR 15 #define GCC_BLSP1_BCR 16 #define GCC_BLSP1_QUP1_BCR 17 #define GCC_BLSP1_UART1_BCR 18 #define GCC_BLSP1_QUP2_BCR 19 #define GCC_BLSP1_UART2_BCR 20 #define GCC_BLSP1_QUP3_BCR 21 #define GCC_BLSP1_UART3_BCR 22 #define GCC_BLSP1_QUP4_BCR 23 #define GCC_BLSP1_UART4_BCR 24 #define GCC_BLSP1_QUP5_BCR 25 #define GCC_BLSP1_UART5_BCR 26 #define GCC_BLSP1_QUP6_BCR 27 #define GCC_BLSP1_UART6_BCR 28 #define GCC_BLSP2_BCR 29 #define GCC_BLSP2_QUP1_BCR 30 #define GCC_BLSP2_UART1_BCR 31 #define GCC_BLSP2_QUP2_BCR 32 #define GCC_BLSP2_UART2_BCR 33 #define GCC_BLSP2_QUP3_BCR 34 #define GCC_BLSP2_UART3_BCR 35 #define GCC_BLSP2_QUP4_BCR 36 #define GCC_BLSP2_UART4_BCR 37 #define GCC_BLSP2_QUP5_BCR 38 #define GCC_BLSP2_UART5_BCR 39 #define GCC_BLSP2_QUP6_BCR 40 #define GCC_BLSP2_UART6_BCR 41 #define GCC_PDM_BCR 42 #define GCC_BAM_DMA_BCR 43 #define GCC_TSIF_BCR 44 #define GCC_TCSR_BCR 45 #define GCC_BOOT_ROM_BCR 46 #define GCC_MSG_RAM_BCR 47 #define GCC_TLMM_BCR 48 #define GCC_MPM_BCR 49 #define GCC_SEC_CTRL_BCR 50 #define GCC_SPMI_BCR 51 #define GCC_SPDM_BCR 52 #define GCC_CE1_BCR 53 #define GCC_CE2_BCR 54 #define GCC_BIMC_BCR 55 #define GCC_MPM_NON_AHB_RESET 56 #define GCC_MPM_AHB_RESET 57 #define GCC_SNOC_BUS_TIMEOUT0_BCR 58 #define GCC_SNOC_BUS_TIMEOUT2_BCR 59 #define GCC_PNOC_BUS_TIMEOUT0_BCR 60 #define GCC_PNOC_BUS_TIMEOUT1_BCR 61 #define GCC_PNOC_BUS_TIMEOUT2_BCR 62 #define GCC_PNOC_BUS_TIMEOUT3_BCR 63 #define GCC_PNOC_BUS_TIMEOUT4_BCR 64 #define GCC_CNOC_BUS_TIMEOUT0_BCR 65 #define GCC_CNOC_BUS_TIMEOUT1_BCR 66 #define GCC_CNOC_BUS_TIMEOUT2_BCR 67 #define GCC_CNOC_BUS_TIMEOUT3_BCR 68 #define GCC_CNOC_BUS_TIMEOUT4_BCR 69 #define GCC_CNOC_BUS_TIMEOUT5_BCR 70 #define GCC_CNOC_BUS_TIMEOUT6_BCR 71 #define GCC_DEHR_BCR 72 #define GCC_RBCPR_BCR 73 #define GCC_MSS_RESTART 74 #define GCC_LPASS_RESTART 75 #define GCC_WCSS_RESTART 76 #define GCC_VENUS_RESTART 77 #endif message (<a href='/cgit.cgi/linux/net-next.git/log/fs/btrfs/file.c?id=b05c76a1f8fe708cd998042a5b0479aef7f2e70b&showmsg=1'>Expand</a>)</th><th class='left'>Author</th><th class='left'>Files</th><th class='left'>Lines</th></tr> f12afe53b2a7'>ci_hdrc_usb2.c</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id' value='5cad24d835772f9f709971a8d6fcf12afe53b2a7'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'> <tr><th>author</th><td>Jean-Nicolas Graux <jean-nicolas.graux@st.com></td><td class='right'>2017-02-07 12:12:41 +0100</td></tr> <tr><th>committer</th><td>Ulf Hansson <ulf.hansson@linaro.org></td><td class='right'>2017-02-08 12:22:27 +0100</td></tr> <tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/drivers/usb/chipidea/ci_hdrc_usb2.c?id=5cad24d835772f9f709971a8d6fcf12afe53b2a7'>5cad24d835772f9f709971a8d6fcf12afe53b2a7</a> (<a href='/cgit.cgi/linux/net-next.git/patch/drivers/usb/chipidea/ci_hdrc_usb2.c?id=5cad24d835772f9f709971a8d6fcf12afe53b2a7'>patch</a>)</td></tr> <tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?id=5cad24d835772f9f709971a8d6fcf12afe53b2a7'>0c1a8bc700c3c219c45ca05dbc5ce3df6be89813</a> /<a href='/cgit.cgi/linux/net-next.git/tree/drivers/usb/chipidea/ci_hdrc_usb2.c?id=5cad24d835772f9f709971a8d6fcf12afe53b2a7'>drivers/usb/chipidea/ci_hdrc_usb2.c</a></td></tr> <tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/drivers/usb/chipidea/ci_hdrc_usb2.c?id=d5adbfcd5f7bcc6fa58a41c5c5ada0e5c826ce2c'>d5adbfcd5f7bcc6fa58a41c5c5ada0e5c826ce2c</a> (<a href='/cgit.cgi/linux/net-next.git/diff/drivers/usb/chipidea/ci_hdrc_usb2.c?id=5cad24d835772f9f709971a8d6fcf12afe53b2a7&id2=d5adbfcd5f7bcc6fa58a41c5c5ada0e5c826ce2c'>diff</a>)</td></tr></table> <div class='commit-subject'>mmc: mmci: avoid clearing ST Micro busy end interrupt mistakenly</div><div class='commit-msg'>This fixes a race condition that may occur whenever ST micro busy end interrupt is raised just after being unmasked but before leaving mmci interrupt context. A dead-lock has been found if connecting mmci ST Micro variant whose amba id is 0x10480180 to some new eMMC that supports internal caches. Whenever mmci driver enables cache control by programming eMMC's EXT_CSD register, block driver may request to flush the eMMC internal caches causing mmci driver to send a MMC_SWITCH command to the card with FLUSH_CACHE operation. And because busy end interrupt may be mistakenly cleared while not yet processed, this mmc request may never complete. As a result, mmcqd task may be stuck forever. Here is an instance caught by lockup detector which shows that mmcqd task was hung while waiting for mmc_flush_cache command to complete: .. [ 240.251595] INFO: task mmcqd/1:52 blocked for more than 120 seconds. [ 240.257973] Not tainted 4.1.13-00510-g9d91424 #2 [ 240.263109] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 240.270955] mmcqd/1 D c047504c 0 52 2 0x00000000 [ 240.277359] [<c047504c>] (__schedule) from [<c04754a0>] (schedule+0x40/0x98) [ 240.284418] [<c04754a0>] (schedule) from [<c0477d40>] (schedule_timeout+0x148/0x188) [ 240.292191] [<c0477d40>] (schedule_timeout) from [<c0476040>] (wait_for_common+0xa4/0x170) [ 240.300491] [<c0476040>] (wait_for_common) from [<c02efc1c>] (mmc_wait_for_req_done+0x4c/0x13c) [ 240.309224] [<c02efc1c>] (mmc_wait_for_req_done) from [<c02efd90>] (mmc_wait_for_cmd+0x64/0x84) [ 240.317953] [<c02efd90>] (mmc_wait_for_cmd) from [<c02f5b14>] (__mmc_switch+0xa4/0x2a8) [ 240.325964] [<c02f5b14>] (__mmc_switch) from [<c02f5d40>] (mmc_switch+0x28/0x30) [ 240.333389] [<c02f5d40>] (mmc_switch) from [<c02f0984>] (mmc_flush_cache+0x54/0x80) [ 240.341073] [<c02f0984>] (mmc_flush_cache) from [<c02ff0c4>] (mmc_blk_issue_rq+0x114/0x4e8) [ 240.349459] [<c02ff0c4>] (mmc_blk_issue_rq) from [<c03008d4>] (mmc_queue_thread+0xc0/0x180) [ 240.357844] [<c03008d4>] (mmc_queue_thread) from [<c003cf90>] (kthread+0xdc/0xf4) [ 240.365339] [<c003cf90>] (kthread) from [<c0010068>] (ret_from_fork+0x14/0x2c) .. .. [ 240.664311] INFO: task partprobe:564 blocked for more than 120 seconds. [ 240.670943] Not tainted 4.1.13-00510-g9d91424 #2 [ 240.676078] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 240.683922] partprobe D c047504c 0 564 486 0x00000000 [ 240.690318] [<c047504c>] (__schedule) from [<c04754a0>] (schedule+0x40/0x98) [ 240.697396] [<c04754a0>] (schedule) from [<c0477d40>] (schedule_timeout+0x148/0x188) [ 240.705149] [<c0477d40>] (schedule_timeout) from [<c0476040>] (wait_for_common+0xa4/0x170) [ 240.713446] [<c0476040>] (wait_for_common) from [<c01f3300>] (submit_bio_wait+0x58/0x64) [ 240.721571] [<c01f3300>] (submit_bio_wait) from [<c01fbbd8>] (blkdev_issue_flush+0x60/0x88) [ 240.729957] [<c01fbbd8>] (blkdev_issue_flush) from [<c010ff84>] (blkdev_fsync+0x34/0x44) [ 240.738083] [<c010ff84>] (blkdev_fsync) from [<c0109594>] (do_fsync+0x3c/0x64) [ 240.745319] [<c0109594>] (do_fsync) from [<c000ffc0>] (ret_fast_syscall+0x0/0x3c) .. Here is the detailed sequence showing when this issue may happen: 1) At probe time, mmci device is initialized and card busy detection based on DAT[0] monitoring is enabled. 2) Later during run time, since card reported to support internal caches, a MMCI_SWITCH command is sent to eMMC device with FLUSH_CACHE operation. On receiving this command, eMMC may enter busy state (for a relatively short time in the case of the dead-lock). 3) Then mmci interrupt is raised and mmci_irq() is called: MMCISTATUS register is read and is equal to 0x01000440. So the following status bits are set: - MCI_CMDRESPEND (= 6) - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is 0x3FF, status variable is set to 0x00000040 and BIT MCI_CMDRESPEND is cleared by writing MMCICLEAR register. Then mmci_cmd_irq() is called. Considering the following conditions: - host->busy_status is 0, - this is a "busy response", - reading again MMCISTATUS register gives 0x1000400, MMCIMASK0 is updated to unmask MCI_ST_BUSYEND bit. Thus, MMCIMASK0 is set to 0x010003FF and host->busy_status is set to wait for busy end completion. Back again in status loop of mmci_irq(), we quickly go through mmci_data_irq() as there are no data in that case. And we finally go through following test at the end of while(status) loop: /* * Don't poll for busy completion in irq context. */ if (host->variant->busy_detect && host->busy_status) status &= ~host->variant->busy_detect_flag; Because status variable is not yet null (is equal to 0x40), we do not leave interrupt context yet but we loop again into while(status) loop. So we run across following steps: a) MMCISTATUS register is read again and this time is equal to 0x01000400. So that following bits are set: - MCI_DATABLOCKEND (= 10) - MCI_ST_CARDBUSY (= 24) Since MMCIMASK0 register is equal to 0x010003FF: b) status variable is set to 0x01000000. c) MCI_ST_CARDBUSY bit is cleared by writing MMCICLEAR register. Then, mmci_cmd_irq() is called one more time. Since host->busy_status is set and that MCI_ST_CARDBUSY is set in status variable, we just return from this function. Back again in mmci_irq(), status variable is set to 0 and we finally leave the while(status) loop. As a result we leave interrupt context, waiting for busy end interrupt event. Now, consider that busy end completion is raised IN BETWEEN steps 3.a) and 3.c). In such a case, we may mistakenly clear busy end interrupt at step 3.c) while it has not yet been processed. This will result in mmc command to wait forever for a busy end completion that will never happen. To fix the problem, this patch implements the following changes: Considering that the mmci seems to be triggering the IRQ on both edges while monitoring DAT0 for busy completion and that same status bit is used to monitor start and end of busy detection, special care must be taken to make sure that both start and end interrupts are always cleared one after the other. 1) Clearing of card busy bit is moved in mmc_cmd_irq() function where unmasking of busy end bit is effectively handled. 2) Just before unmasking busy end event, busy start event is cleared by writing card busy bit in MMCICLEAR register. 3) Finally, once we are no more busy with a command, busy end event is cleared writing again card busy bit in MMCICLEAR register. This patch has been tested with the ST Accordo5 machine, not yet supported upstream but relies on the mmci driver. Signed-off-by: Sarang Mairal <sarang.mairal@garmin.com> Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> </div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=5cad24d835772f9f709971a8d6fcf12afe53b2a7'>Diffstat</a> (limited to 'drivers/usb/chipidea/ci_hdrc_usb2.c')</div><table summary='diffstat' class='diffstat'>