/* * Copyright (c) 2014, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H #define _DT_BINDINGS_RESET_APQ_MMCC_8084_H #define MMSS_SPDM_RESET 0 #define MMSS_SPDM_RM_RESET 1 #define VENUS0_RESET 2 #define VPU_RESET 3 #define MDSS_RESET 4 #define AVSYNC_RESET 5 #define CAMSS_PHY0_RESET 6 #define CAMSS_PHY1_RESET 7 #define CAMSS_PHY2_RESET 8 #define CAMSS_CSI0_RESET 9 #define CAMSS_CSI0PHY_RESET 10 #define CAMSS_CSI0RDI_RESET 11 #define CAMSS_CSI0PIX_RESET 12 #define CAMSS_CSI1_RESET 13 #define CAMSS_CSI1PHY_RESET 14 #define CAMSS_CSI1RDI_RESET 15 #define CAMSS_CSI1PIX_RESET 16 #define CAMSS_CSI2_RESET 17 #define CAMSS_CSI2PHY_RESET 18 #define CAMSS_CSI2RDI_RESET 19 #define CAMSS_CSI2PIX_RESET 20 #define CAMSS_CSI3_RESET 21 #define CAMSS_CSI3PHY_RESET 22 #define CAMSS_CSI3RDI_RESET 23 #define CAMSS_CSI3PIX_RESET 24 #define CAMSS_ISPIF_RESET 25 #define CAMSS_CCI_RESET 26 #define CAMSS_MCLK0_RESET 27 #define CAMSS_MCLK1_RESET 28 #define CAMSS_MCLK2_RESET 29 #define CAMSS_MCLK3_RESET 30 #define CAMSS_GP0_RESET 31 #define CAMSS_GP1_RESET 32 #define CAMSS_TOP_RESET 33 #define CAMSS_AHB_RESET 34 #define CAMSS_MICRO_RESET 35 #define CAMSS_JPEG_RESET 36 #define CAMSS_VFE_RESET 37 #define CAMSS_CSI_VFE0_RESET 38 #define CAMSS_CSI_VFE1_RESET 39 #define OXILI_RESET 40 #define OXILICX_RESET 41 #define OCMEMCX_RESET 42 #define MMSS_RBCRP_RESET 43 #define MMSSNOCAHB_RESET 44 #define MMSSNOCAXI_RESET 45 #endif db970aace7f0'>commitdiff
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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2017-01-29 15:07:34 +0300
committerDavid S. Miller <davem@davemloft.net>2017-01-30 22:05:43 -0500
commit1a0bee6c1e788218fd1d141db320db970aace7f0 (patch)
tree46c4116bc8ef4a7df718516a648597d9e21c15f1 /include/sound/dmaengine_pcm.h
parent63c190429020a9701b42887ac22c28f287f1762f (diff)
sh_eth: rename EESIPR bits
Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/sound/dmaengine_pcm.h')