#ifndef __DT_FSL_IMX_AUDMUX_H #define __DT_FSL_IMX_AUDMUX_H #define MX27_AUDMUX_HPCR1_SSI0 0 #define MX27_AUDMUX_HPCR2_SSI1 1 #define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 #define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 #define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 #define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 #define MX31_AUDMUX_PORT1_SSI0 0 #define MX31_AUDMUX_PORT2_SSI1 1 #define MX31_AUDMUX_PORT3_SSI_PINS_3 2 #define MX31_AUDMUX_PORT4_SSI_PINS_4 3 #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 #define MX31_AUDMUX_PORT7_SSI_PINS_7 6 #define MX51_AUDMUX_PORT1_SSI0 0 #define MX51_AUDMUX_PORT2_SSI1 1 #define MX51_AUDMUX_PORT3 2 #define MX51_AUDMUX_PORT4 3 #define MX51_AUDMUX_PORT5 4 #define MX51_AUDMUX_PORT6 5 #define MX51_AUDMUX_PORT7 6 /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ #define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) #define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) #define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10) #define IMX_AUDMUX_V1_PCR_SYN (1 << 12) #define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) #define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) #define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24) #define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25) #define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) #define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30) #define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31) /* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ #define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31) #define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) #define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) #define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) #define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21) #define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) #define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) #define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) #define IMX_AUDMUX_V2_PTCR_SYN (1 << 11) #define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) #define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12) #define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) #define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) #endif /* __DT_FSL_IMX_AUDMUX_H */ od='get' action='/cgit.cgi/linux/net-next.git/log/include/crypto/padlock.h'>
path: root/include/crypto/padlock.h
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authorThomas Gleixner <tglx@linutronix.de>2017-01-31 09:37:34 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-31 21:47:58 +0100
commit0becc0ae5b42828785b589f686725ff5bc3b9b25 (patch)
treebe6d0e1f37c38ed0a7dd5da2d4b1e93f0fb43101 /net/wireless/util.c
parent24c2503255d35c269b67162c397a1a1c1e02f6ce (diff)
x86/mce: Make timer handling more robust
Erik reported that on a preproduction hardware a CMCI storm triggers the BUG_ON in add_timer_on(). The reason is that the per CPU MCE timer is started by the CMCI logic before the MCE CPU hotplug callback starts the timer with add_timer_on(). So the timer is already queued which triggers the BUG. Using add_timer_on() is pretty pointless in this code because the timer is strictlty per CPU, initialized as pinned and all operations which arm the timer happen on the CPU to which the timer belongs. Simplify the whole machinery by using mod_timer() instead of add_timer_on() which avoids the problem because mod_timer() can handle already queued timers. Use __start_timer() everywhere so the earliest armed expiry time is preserved. Reported-by: Erik Veijola <erik.veijola@intel.com> Tested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@alien8.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/alpine.DEB.2.20.1701310936080.3457@nanos Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'net/wireless/util.c')