/* * s3c24xx/s3c64xx SoC series Camera Interface (CAMIF) driver * * Copyright (C) 2012 Sylwester Nawrocki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef MEDIA_S3C_CAMIF_ #define MEDIA_S3C_CAMIF_ #include #include /** * struct s3c_camif_sensor_info - an image sensor description * @i2c_board_info: pointer to an I2C sensor subdevice board info * @clock_frequency: frequency of the clock the host provides to a sensor * @mbus_type: media bus type * @i2c_bus_num: i2c control bus id the sensor is attached to * @flags: the parallel bus flags defining signals polarity (V4L2_MBUS_*) * @use_field: 1 if parallel bus FIELD signal is used (only s3c64xx) */ struct s3c_camif_sensor_info { struct i2c_board_info i2c_board_info; unsigned long clock_frequency; enum v4l2_mbus_type mbus_type; u16 i2c_bus_num; u16 flags; u8 use_field; }; struct s3c_camif_plat_data { struct s3c_camif_sensor_info sensor; int (*gpio_get)(void); int (*gpio_put)(void); }; /* Platform default helper functions */ int s3c_camif_gpio_get(void); int s3c_camif_gpio_put(void); #endif /* MEDIA_S3C_CAMIF_ */ on> net-next plumbingsTobias Klauser
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /tools/testing/selftests/timers/raw_skew.c
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'tools/testing/selftests/timers/raw_skew.c')