/*
* adv7183.h - definition for adv7183 inputs and outputs
*
* Copyright (c) 2011 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _ADV7183_H_
#define _ADV7183_H_
/* ADV7183 HW inputs */
#define ADV7183_COMPOSITE0 0 /* CVBS in on AIN1 */
#define ADV7183_COMPOSITE1 1 /* CVBS in on AIN2 */
#define ADV7183_COMPOSITE2 2 /* CVBS in on AIN3 */
#define ADV7183_COMPOSITE3 3 /* CVBS in on AIN4 */
#define ADV7183_COMPOSITE4 4 /* CVBS in on AIN5 */
#define ADV7183_COMPOSITE5 5 /* CVBS in on AIN6 */
#define ADV7183_COMPOSITE6 6 /* CVBS in on AIN7 */
#define ADV7183_COMPOSITE7 7 /* CVBS in on AIN8 */
#define ADV7183_COMPOSITE8 8 /* CVBS in on AIN9 */
#define ADV7183_COMPOSITE9 9 /* CVBS in on AIN10 */
#define ADV7183_COMPOSITE10 10 /* CVBS in on AIN11 */
#define ADV7183_SVIDEO0 11 /* Y on AIN1, C on AIN4 */
#define ADV7183_SVIDEO1 12 /* Y on AIN2, C on AIN5 */
#define ADV7183_SVIDEO2 13 /* Y on AIN3, C on AIN6 */
#define ADV7183_COMPONENT0 14 /* Y on AIN1, Pr on AIN4, Pb on AIN5 */
#define ADV7183_COMPONENT1 15 /* Y on AIN2, Pr on AIN3, Pb on AIN6 */
/* ADV7183 HW outputs */
#define ADV7183_8BIT_OUT 0
#define ADV7183_16BIT_OUT 1
#endif
de/crypto/hash.h?h=nds-private-remove'>logtreecommitdiff
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of
the root of the PCIe hierarchy. For the topmost link, this points to
itself (link->root = link). For others, we copy the pointer from the
parent (link->root = link->parent->root).
Previously we recognized that Root Ports originated PCIe hierarchies, but
we treated PCI/PCI-X to PCIe Bridges as being in the middle of the
hierarchy, and when we tried to copy the pointer from link->parent->root,
there was no parent, and we dereferenced a NULL pointer:
BUG: unable to handle kernel NULL pointer dereference at 0000000000000090
IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820
Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just
like Root Ports do, so link->root for these devices should also point to
itself.
Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411
Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181
Tested-by: lists@ssl-mail.com
Tested-by: Jayachandran C. <jnair@caviumnetworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v4.2+