/*
    cs53l32a.h - definition for cs53l32a inputs and outputs

    Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#ifndef _CS53L32A_H_
#define _CS53L32A_H_

/* There are 2 physical inputs, but the second input can be
   placed in two modes, the first mode bypasses the PGA (gain),
   the second goes through the PGA. Hence there are three
   possible inputs to choose from. */

/* CS53L32A HW inputs */
#define CS53L32A_IN0 0
#define CS53L32A_IN1 1
#define CS53L32A_IN2 2

#endif
nds-private-remove'>nds-private-remove</option>
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<tr><td class='sub'>net-next plumbings</td><td class='sub right'>Tobias Klauser</td></tr></table>
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<div class='path'>path: <a href='/cgit.cgi/linux/net-next.git/diff/?id=9da96f99f15169b8bf77a1f27ed6d926f82ea59f&amp;id2=0aa0313f9d576affd7747cc3f179feb097d28990'>root</a>/<a href='/cgit.cgi/linux/net-next.git/diff/include?id=9da96f99f15169b8bf77a1f27ed6d926f82ea59f&amp;id2=0aa0313f9d576affd7747cc3f179feb097d28990'>include</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id' value='9da96f99f15169b8bf77a1f27ed6d926f82ea59f'/><input type='hidden' name='id2' value='0aa0313f9d576affd7747cc3f179feb097d28990'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=9da96f99f15169b8bf77a1f27ed6d926f82ea59f&amp;id2=0aa0313f9d576affd7747cc3f179feb097d28990'>Diffstat</a> (limited to 'include')</div><table summary='diffstat' class='diffstat'>ref='/cgit.cgi/linux/net-next.git/commit/net/sctp/ipv6.c?id=c26665ab5c49ad3e142e0f054ca3204f259ba09c'>c26665ab5c49ad3e142e0f054ca3204f259ba09c</a> (<a href='/cgit.cgi/linux/net-next.git/patch/net/sctp/ipv6.c?id=c26665ab5c49ad3e142e0f054ca3204f259ba09c'>patch</a>)</td></tr>
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<div class='commit-subject'>x86/microcode/intel: Drop stashed AP patch pointer optimization</div><div class='commit-msg'>This was meant to save us the scanning of the microcode containter in
the initrd since the first AP had already done that but it can also hurt
us:

Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for
example) which updates the microcode on the BSP but since the microcode
engine is shared between the two threads, the update on CPU1 doesn't
happen because it has already happened on CPU0 and we don't find a newer
microcode revision on CPU1.

Which doesn't set the intel_ucode_patch pointer and at initrd
jettisoning time we don't save the microcode patch for later
application.

Now, when we suspend to RAM, the loaded microcode gets cleared so we
need to reload but there's no patch saved in the cache.

Removing the optimization fixes this issue and all is fine and dandy.

Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading")
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=c26665ab5c49ad3e142e0f054ca3204f259ba09c'>Diffstat</a> (limited to 'net/sctp/ipv6.c')</div><table summary='diffstat' class='diffstat'>