/* * include/media/i2c/lm3646.h * * Copyright (C) 2014 Texas Instruments * * Contact: Daniel Jeong * Ldd-Mlp * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. */ #ifndef __LM3646_H__ #define __LM3646_H__ #include #define LM3646_NAME "lm3646" #define LM3646_I2C_ADDR_REV1 (0x67) #define LM3646_I2C_ADDR_REV0 (0x63) /* TOTAL FLASH Brightness Max * min 93350uA, step 93750uA, max 1499600uA */ #define LM3646_TOTAL_FLASH_BRT_MIN 93350 #define LM3646_TOTAL_FLASH_BRT_STEP 93750 #define LM3646_TOTAL_FLASH_BRT_MAX 1499600 #define LM3646_TOTAL_FLASH_BRT_uA_TO_REG(a) \ ((a) < LM3646_TOTAL_FLASH_BRT_MIN ? 0 : \ ((((a) - LM3646_TOTAL_FLASH_BRT_MIN) / LM3646_TOTAL_FLASH_BRT_STEP))) /* TOTAL TORCH Brightness Max * min 23040uA, step 23430uA, max 187100uA */ #define LM3646_TOTAL_TORCH_BRT_MIN 23040 #define LM3646_TOTAL_TORCH_BRT_STEP 23430 #define LM3646_TOTAL_TORCH_BRT_MAX 187100 #define LM3646_TOTAL_TORCH_BRT_uA_TO_REG(a) \ ((a) < LM3646_TOTAL_TORCH_BRT_MIN ? 0 : \ ((((a) - LM3646_TOTAL_TORCH_BRT_MIN) / LM3646_TOTAL_TORCH_BRT_STEP))) /* LED1 FLASH Brightness * min 23040uA, step 11718uA, max 1499600uA */ #define LM3646_LED1_FLASH_BRT_MIN 23040 #define LM3646_LED1_FLASH_BRT_STEP 11718 #define LM3646_LED1_FLASH_BRT_MAX 1499600 #define LM3646_LED1_FLASH_BRT_uA_TO_REG(a) \ ((a) <= LM3646_LED1_FLASH_BRT_MIN ? 0 : \ ((((a) - LM3646_LED1_FLASH_BRT_MIN) / LM3646_LED1_FLASH_BRT_STEP))+1) /* LED1 TORCH Brightness * min 2530uA, step 1460uA, max 187100uA */ #define LM3646_LED1_TORCH_BRT_MIN 2530 #define LM3646_LED1_TORCH_BRT_STEP 1460 #define LM3646_LED1_TORCH_BRT_MAX 187100 #define LM3646_LED1_TORCH_BRT_uA_TO_REG(a) \ ((a) <= LM3646_LED1_TORCH_BRT_MIN ? 0 : \ ((((a) - LM3646_LED1_TORCH_BRT_MIN) / LM3646_LED1_TORCH_BRT_STEP))+1) /* FLASH TIMEOUT DURATION * min 50ms, step 50ms, max 400ms */ #define LM3646_FLASH_TOUT_MIN 50 #define LM3646_FLASH_TOUT_STEP 50 #define LM3646_FLASH_TOUT_MAX 400 #define LM3646_FLASH_TOUT_ms_TO_REG(a) \ ((a) <= LM3646_FLASH_TOUT_MIN ? 0 : \ (((a) - LM3646_FLASH_TOUT_MIN) / LM3646_FLASH_TOUT_STEP)) /* struct lm3646_platform_data * * @flash_timeout: flash timeout * @led1_flash_brt: led1 flash mode brightness, uA * @led1_torch_brt: led1 torch mode brightness, uA */ struct lm3646_platform_data { u32 flash_timeout; u32 led1_flash_brt; u32 led1_torch_brt; }; #endif /* __LM3646_H__ */
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /tools/testing/selftests/vm/hugepage-shm.c
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'tools/testing/selftests/vm/hugepage-shm.c')