/* * Copyright (C) ST-Ericsson AB 2010 * Author: Daniel Martensson / Daniel.Martensson@stericsson.com * License terms: GNU General Public License (GPL) version 2 */ #ifndef CAIF_SPI_H_ #define CAIF_SPI_H_ #include #define SPI_CMD_WR 0x00 #define SPI_CMD_RD 0x01 #define SPI_CMD_EOT 0x02 #define SPI_CMD_IND 0x04 #define SPI_DMA_BUF_LEN 8192 #define WL_SZ 2 /* 16 bits. */ #define SPI_CMD_SZ 4 /* 32 bits. */ #define SPI_IND_SZ 4 /* 32 bits. */ #define SPI_XFER 0 #define SPI_SS_ON 1 #define SPI_SS_OFF 2 #define SPI_TERMINATE 3 /* Minimum time between different levels is 50 microseconds. */ #define MIN_TRANSITION_TIME_USEC 50 /* Defines for calculating duration of SPI transfers for a particular * number of bytes. */ #define SPI_MASTER_CLK_MHZ 13 #define SPI_XFER_TIME_USEC(bytes, clk) (((bytes) * 8) / clk) /* Normally this should be aligned on the modem in order to benefit from full * duplex transfers. However a size of 8188 provokes errors when running with * the modem. These errors occur when packet sizes approaches 4 kB of data. */ #define CAIF_MAX_SPI_FRAME 4092 /* Maximum number of uplink CAIF frames that can reside in the same SPI frame. * This number should correspond with the modem setting. The application side * CAIF accepts any number of embedded downlink CAIF frames. */ #define CAIF_MAX_SPI_PKTS 9 /* Decides if SPI buffers should be prefilled with 0xFF pattern for easier * debugging. Both TX and RX buffers will be filled before the transfer. */ #define CFSPI_DBG_PREFILL 0 /* Structure describing a SPI transfer. */ struct cfspi_xfer { u16 tx_dma_len; u16 rx_dma_len; void *va_tx[2]; dma_addr_t pa_tx[2]; void *va_rx; dma_addr_t pa_rx; }; /* Structure implemented by the SPI interface. */ struct cfspi_ifc { void (*ss_cb) (bool assert, struct cfspi_ifc *ifc); void (*xfer_done_cb) (struct cfspi_ifc *ifc); void *priv; }; /* Structure implemented by SPI clients. */ struct cfspi_dev { int (*init_xfer) (struct cfspi_xfer *xfer, struct cfspi_dev *dev); void (*sig_xfer) (bool xfer, struct cfspi_dev *dev); struct cfspi_ifc *ifc; char *name; u32 clk_mhz; void *priv; }; /* Enumeration describing the CAIF SPI state. */ enum cfspi_state { CFSPI_STATE_WAITING = 0, CFSPI_STATE_AWAKE, CFSPI_STATE_FETCH_PKT, CFSPI_STATE_GET_NEXT, CFSPI_STATE_INIT_XFER, CFSPI_STATE_WAIT_ACTIVE, CFSPI_STATE_SIG_ACTIVE, CFSPI_STATE_WAIT_XFER_DONE, CFSPI_STATE_XFER_DONE, CFSPI_STATE_WAIT_INACTIVE, CFSPI_STATE_SIG_INACTIVE, CFSPI_STATE_DELIVER_PKT, CFSPI_STATE_MAX, }; /* Structure implemented by SPI physical interfaces. */ struct cfspi { struct caif_dev_common cfdev; struct net_device *ndev; struct platform_device *pdev; struct sk_buff_head qhead; struct sk_buff_head chead; u16 cmd; u16 tx_cpck_len; u16 tx_npck_len; u16 rx_cpck_len; u16 rx_npck_len; struct cfspi_ifc ifc; struct cfspi_xfer xfer; struct cfspi_dev *dev; unsigned long state; struct work_struct work; struct workqueue_struct *wq; struct list_head list; int flow_off_sent; u32 qd_low_mark; u32 qd_high_mark; struct completion comp; wait_queue_head_t wait; spinlock_t lock; bool flow_stop; bool slave; bool slave_talked; #ifdef CONFIG_DEBUG_FS enum cfspi_state dbg_state; u16 pcmd; u16 tx_ppck_len; u16 rx_ppck_len; struct dentry *dbgfs_dir; struct dentry *dbgfs_state; struct dentry *dbgfs_frame; #endif /* CONFIG_DEBUG_FS */ }; extern int spi_frm_align; extern int spi_up_head_align; extern int spi_up_tail_align; extern int spi_down_head_align; extern int spi_down_tail_align; extern struct platform_driver cfspi_spi_driver; void cfspi_dbg_state(struct cfspi *cfspi, int state); int cfspi_xmitfrm(struct cfspi *cfspi, u8 *buf, size_t len); int cfspi_xmitlen(struct cfspi *cfspi); int cfspi_rxfrm(struct cfspi *cfspi, u8 *buf, size_t len); int cfspi_spi_remove(struct platform_device *pdev); int cfspi_spi_probe(struct platform_device *pdev); int cfspi_xmitfrm(struct cfspi *cfspi, u8 *buf, size_t len); int cfspi_xmitlen(struct cfspi *cfspi); int cfspi_rxfrm(struct cfspi *cfspi, u8 *buf, size_t len); void cfspi_xfer(struct work_struct *work); #endif /* CAIF_SPI_H_ */ scale,asm9260.h?h=nds-private-remove&id=dfcb7a14866b8c34b2d3a74ae31631e1d4e7f591'>plain -rw-r--r--at91.h751logplain -rw-r--r--ath79-clk.h479logplain -rw-r--r--axis,artpec6-clkctrl.h1112logplain -rw-r--r--bcm-cygnus.h3135logplain -rw-r--r--bcm-ns2.h2915logplain -rw-r--r--bcm-nsp.h2148logplain -rw-r--r--bcm21664.h1984logplain -rw-r--r--bcm281xx.h2456logplain -rw-r--r--bcm2835-aux.h635logplain -rw-r--r--bcm2835.h1962logplain -rw-r--r--berlin2.h1034logplain -rw-r--r--berlin2q.h695logplain -rw-r--r--clps711x-clock.h718logplain -rw-r--r--efm32-cmu.h1112logplain -rw-r--r--exynos-audss-clk.h597logplain -rw-r--r--exynos3250.h9083logplain -rw-r--r--exynos4.h8284logplain -rw-r--r--exynos4415.h9828logplain -rw-r--r--exynos5250.h4616logplain -rw-r--r--exynos5260-clk.h14876logplain -rw-r--r--exynos5410.h1689logplain -rw-r--r--exynos5420.h6857logplain -rw-r--r--exynos5433.h45372logplain -rw-r--r--exynos5440.h1141logplain -rw-r--r--exynos7-clk.h5281logplain -rw-r--r--gxbb-aoclkc.h2866logplain -rw-r--r--gxbb-clkc.h592logplain -rw-r--r--hi3516cv300-clock.h1668logplain -rw-r--r--hi3519-clock.h1328logplain -rw-r--r--hi3620-clock.h4496logplain -rw-r--r--hi6220-clock.h4508logplain -rw-r--r--hip04-clock.h1137logplain -rw-r--r--histb-clock.h2012logplain -rw-r--r--hix5hd2-clock.h2415logplain -rw-r--r--imx1-clock.h1055logplain -rw-r--r--imx21-clock.h2461logplain -rw-r--r--imx27-clock.h3494logplain -rw-r--r--imx5-clock.h7212logplain -rw-r--r--imx6qdl-clock.h9593logplain -rw-r--r--imx6sl-clock.h5849logplain -rw-r--r--imx6sx-clock.h9099logplain -rw-r--r--imx6ul-clock.h8203logplain -rw-r--r--imx7d-clock.h15974logplain -rw-r--r--jz4740-cgu.h1028logplain -rw-r--r--jz4780-cgu.h2470logplain -rw-r--r--lpc18xx-ccu.h2134logplain -rw-r--r--lpc18xx-cgu.h1142logplain -rw-r--r--lpc32xx-clock.h1633logplain -rw-r--r--lsi,axm5516-clks.h974logplain -rw-r--r--marvell,mmp2.h2022logplain -rw-r--r--marvell,pxa168.h1654logplain -rw-r--r--marvell,pxa1928.h1535logplain -rw-r--r--marvell,pxa910.h1598logplain -rw-r--r--maxim,max77620.h632logplain -rw-r--r--maxim,max77686.h648logplain -rw-r--r--maxim,max77802.h630logplain -rw-r--r--meson8b-clkc.h523logplain -rw-r--r--microchip,pic32-clock.h1150logplain -rw-r--r--mpc512x-clock.h2236logplain -rw-r--r--mt2701-clk.h13832logplain -rw-r--r--mt8135-clk.h5641logplain -rw-r--r--mt8173-clk.h9293logplain -rw-r--r--oxsemi,ox810se.h1002logplain -rw-r--r--oxsemi,ox820.h1203logplain -rw-r--r--pistachio-clk.h4863logplain -rw-r--r--pxa-clock.h1715logplain -rw-r--r--qcom,gcc-apq8084.h12872logplain -rw-r--r--qcom,gcc-ipq4019.h5423logplain -rw-r--r--qcom,gcc-ipq806x.h8574logplain -rw-r--r--qcom,gcc-mdm9615.h9497logplain -rw-r--r--qcom,gcc-msm8660.h7932logplain -rw-r--r--qcom,gcc-msm8916.h6190logplain -rw-r--r--qcom,gcc-msm8960.h9342logplain -rw-r--r--qcom,gcc-msm8974.h12340logplain -rw-r--r--qcom,gcc-msm8994.h4858logplain -rw-r--r--qcom,gcc-msm8996.h12575logplain -rw-r--r--qcom,lcc-ipq806x.h899logplain -rw-r--r--qcom,lcc-mdm9615.h1701logplain -rw-r--r--qcom,lcc-msm8960.h1616logplain -rw-r--r--qcom,mmcc-apq8084.h5722logplain -rw-r--r--qcom,mmcc-msm8960.h4109logplain -rw-r--r--qcom,mmcc-msm8974.h5223logplain -rw-r--r--qcom,mmcc-msm8996.h9403logplain -rw-r--r--qcom,rpmcc.h2101logplain -rw-r--r--r7s72100-clock.h1218logplain -rw-r--r--r8a73a4-clock.h1596logplain -rw-r--r--r8a7740-clock.h1992logplain -rw-r--r--r8a7743-cpg-mssr.h1269logplain -rw-r--r--r8a7745-cpg-mssr.h1298logplain -rw-r--r--r8a7778-clock.h1855logplain -rw-r--r--r8a7779-clock.h1647logplain -rw-r--r--r8a7790-clock.h4367logplain -rw-r--r--r8a7791-clock.h4388logplain -rw-r--r--r8a7792-clock.h2562logplain -rw-r--r--r8a7793-clock.h4561logplain -rw-r--r--r8a7794-clock.h3679logplain -rw-r--r--r8a7795-cpg-mssr.h1890logplain -rw-r--r--r8a7796-cpg-mssr.h2066logplain -rw-r--r--renesas-cpg-mssr.h542logplain -rw-r--r--rk1108-cru.h6605logplain -rw-r--r--rk3036-cru.h4584logplain -rw-r--r--rk3066a-cru.h1068logplain -rw-r--r--rk3188-cru-common.h6105logplain -rw-r--r--rk3188-cru.h1435logplain