/* * Copyright (C) ST-Ericsson AB 2010 * Author: Sjur Brendeland * License terms: GNU General Public License (GPL) version 2 */ #ifndef CFCTRL_H_ #define CFCTRL_H_ #include #include /* CAIF Control packet commands */ enum cfctrl_cmd { CFCTRL_CMD_LINK_SETUP = 0, CFCTRL_CMD_LINK_DESTROY = 1, CFCTRL_CMD_LINK_ERR = 2, CFCTRL_CMD_ENUM = 3, CFCTRL_CMD_SLEEP = 4, CFCTRL_CMD_WAKE = 5, CFCTRL_CMD_LINK_RECONF = 6, CFCTRL_CMD_START_REASON = 7, CFCTRL_CMD_RADIO_SET = 8, CFCTRL_CMD_MODEM_SET = 9, CFCTRL_CMD_MASK = 0xf }; /* Channel types */ enum cfctrl_srv { CFCTRL_SRV_DECM = 0, CFCTRL_SRV_VEI = 1, CFCTRL_SRV_VIDEO = 2, CFCTRL_SRV_DBG = 3, CFCTRL_SRV_DATAGRAM = 4, CFCTRL_SRV_RFM = 5, CFCTRL_SRV_UTIL = 6, CFCTRL_SRV_MASK = 0xf }; #define CFCTRL_RSP_BIT 0x20 #define CFCTRL_ERR_BIT 0x10 struct cfctrl_rsp { void (*linksetup_rsp)(struct cflayer *layer, u8 linkid, enum cfctrl_srv serv, u8 phyid, struct cflayer *adapt_layer); void (*linkdestroy_rsp)(struct cflayer *layer, u8 linkid); void (*linkerror_ind)(void); void (*enum_rsp)(void); void (*sleep_rsp)(void); void (*wake_rsp)(void); void (*restart_rsp)(void); void (*radioset_rsp)(void); void (*reject_rsp)(struct cflayer *layer, u8 linkid, struct cflayer *client_layer); }; /* Link Setup Parameters for CAIF-Links. */ struct cfctrl_link_param { enum cfctrl_srv linktype;/* (T3,T0) Type of Channel */ u8 priority; /* (P4,P0) Priority of the channel */ u8 phyid; /* (U2-U0) Physical interface to connect */ u8 endpoint; /* (E1,E0) Endpoint for data channels */ u8 chtype; /* (H1,H0) Channel-Type, applies to * VEI, DEBUG */ union { struct { u8 connid; /* (D7,D0) Video LinkId */ } video; struct { u32 connid; /* (N31,Ngit0) Connection ID used * for Datagram */ } datagram; struct { u32 connid; /* Connection ID used for RFM */ char volume[20]; /* Volume to mount for RFM */ } rfm; /* Configuration for RFM */ struct { u16 fifosize_kb; /* Psock FIFO size in KB */ u16 fifosize_bufs; /* Psock # signal buffers */ char name[16]; /* Name of the PSOCK service */ u8 params[255]; /* Link setup Parameters> */ u16 paramlen; /* Length of Link Setup * Parameters */ } utility; /* Configuration for Utility Links (Psock) */ } u; }; /* This structure is used internally in CFCTRL */ struct cfctrl_request_info { int sequence_no; enum cfctrl_cmd cmd; u8 channel_id; struct cfctrl_link_param param; struct cflayer *client_layer; struct list_head list; }; struct cfctrl { struct cfsrvl serv; struct cfctrl_rsp res; atomic_t req_seq_no; atomic_t rsp_seq_no; struct list_head list; /* Protects from simultaneous access to first_req list */ spinlock_t info_list_lock; #ifndef CAIF_NO_LOOP u8 loop_linkid; int loop_linkused[256]; /* Protects simultaneous access to loop_linkid and loop_linkused */ spinlock_t loop_linkid_lock; #endif }; void cfctrl_enum_req(struct cflayer *cfctrl, u8 physlinkid); int cfctrl_linkup_request(struct cflayer *cfctrl, struct cfctrl_link_param *param, struct cflayer *user_layer); int cfctrl_linkdown_req(struct cflayer *cfctrl, u8 linkid, struct cflayer *client); struct cflayer *cfctrl_create(void); struct cfctrl_rsp *cfctrl_get_respfuncs(struct cflayer *layer); int cfctrl_cancel_req(struct cflayer *layr, struct cflayer *adap_layer); void cfctrl_remove(struct cflayer *layr); #endif /* CFCTRL_H_ */ ut type='hidden' name='h' value='nds-private-remove'/>
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /include/net/seg6.h
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/net/seg6.h')