/* * Copyright (c) 2014 Intel Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #if !defined(OPA_SMI_H) #define OPA_SMI_H #include #include #define OPA_SMP_LID_DATA_SIZE 2016 #define OPA_SMP_DR_DATA_SIZE 1872 #define OPA_SMP_MAX_PATH_HOPS 64 #define OPA_MAX_VLS 32 #define OPA_MAX_SLS 32 #define OPA_MAX_SCS 32 #define OPA_LID_PERMISSIVE cpu_to_be32(0xFFFFFFFF) struct opa_smp { u8 base_version; u8 mgmt_class; u8 class_version; u8 method; __be16 status; u8 hop_ptr; u8 hop_cnt; __be64 tid; __be16 attr_id; __be16 resv; __be32 attr_mod; __be64 mkey; union { struct { uint8_t data[OPA_SMP_LID_DATA_SIZE]; } lid; struct { __be32 dr_slid; __be32 dr_dlid; u8 initial_path[OPA_SMP_MAX_PATH_HOPS]; u8 return_path[OPA_SMP_MAX_PATH_HOPS]; u8 reserved[8]; u8 data[OPA_SMP_DR_DATA_SIZE]; } dr; } route; } __packed; /* Subnet management attributes */ /* ... */ #define OPA_ATTRIB_ID_NODE_DESCRIPTION cpu_to_be16(0x0010) #define OPA_ATTRIB_ID_NODE_INFO cpu_to_be16(0x0011) #define OPA_ATTRIB_ID_PORT_INFO cpu_to_be16(0x0015) #define OPA_ATTRIB_ID_PARTITION_TABLE cpu_to_be16(0x0016) #define OPA_ATTRIB_ID_SL_TO_SC_MAP cpu_to_be16(0x0017) #define OPA_ATTRIB_ID_VL_ARBITRATION cpu_to_be16(0x0018) #define OPA_ATTRIB_ID_SM_INFO cpu_to_be16(0x0020) #define OPA_ATTRIB_ID_CABLE_INFO cpu_to_be16(0x0032) #define OPA_ATTRIB_ID_AGGREGATE cpu_to_be16(0x0080) #define OPA_ATTRIB_ID_SC_TO_SL_MAP cpu_to_be16(0x0082) #define OPA_ATTRIB_ID_SC_TO_VLR_MAP cpu_to_be16(0x0083) #define OPA_ATTRIB_ID_SC_TO_VLT_MAP cpu_to_be16(0x0084) #define OPA_ATTRIB_ID_SC_TO_VLNT_MAP cpu_to_be16(0x0085) /* ... */ #define OPA_ATTRIB_ID_PORT_STATE_INFO cpu_to_be16(0x0087) /* ... */ #define OPA_ATTRIB_ID_BUFFER_CONTROL_TABLE cpu_to_be16(0x008A) /* ... */ struct opa_node_description { u8 data[64]; } __attribute__ ((packed)); struct opa_node_info { u8 base_version; u8 class_version; u8 node_type; u8 num_ports; __be32 reserved; __be64 system_image_guid; __be64 node_guid; __be64 port_guid; __be16 partition_cap; __be16 device_id; __be32 revision; u8 local_port_num; u8 vendor_id[3]; /* network byte order */ } __attribute__ ((packed)); #define OPA_PARTITION_TABLE_BLK_SIZE 32 static inline u8 opa_get_smp_direction(struct opa_smp *smp) { return ib_get_smp_direction((struct ib_smp *)smp); } static inline u8 *opa_get_smp_data(struct opa_smp *smp) { if (smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) return smp->route.dr.data; return smp->route.lid.data; } static inline size_t opa_get_smp_data_size(struct opa_smp *smp) { if (smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) return sizeof(smp->route.dr.data); return sizeof(smp->route.lid.data); } static inline size_t opa_get_smp_header_size(struct opa_smp *smp) { if (smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) return sizeof(*smp) - sizeof(smp->route.dr.data); return sizeof(*smp) - sizeof(smp->route.lid.data); } #endif /* OPA_SMI_H */ ubmit();'>mode:
authorChen-Yu Tsai <wens@csie.org>2016-11-11 11:12:43 +0800
committerMark Brown <broonie@kernel.org>2016-11-11 15:34:45 +0000
commit618c808968852609d2d9f0e5cfc351a4807ef8d0 (patch)
tree01a8d928c06fe7bef488f55bade6ba37b958bb5f /include/acpi/platform
parent1001354ca34179f3db924eb66672442a173147dc (diff)
regulator: axp20x: Fix axp809 ldo_io registration error on cold boot
The maximum supported voltage for ldo_io# is 3.3V, but on cold boot the selector comes up at 0x1f, which maps to 3.8V. This was previously corrected by Allwinner's U-boot, which set all regulators on the PMICs to some pre-configured voltage. With recent progress in U-boot SPL support, this is no longer the case. In any case we should handle this quirk in the kernel driver as well. This invalid setting causes _regulator_get_voltage() to fail with -EINVAL which causes regulator registration to fail when constrains are used: [ 1.054181] vcc-pg: failed to get the current voltage(-22) [ 1.059670] axp20x-regulator axp20x-regulator.0: Failed to register ldo_io0 [ 1.069749] axp20x-regulator: probe of axp20x-regulator.0 failed with error -22 This commits makes the axp20x regulator driver accept the 0x1f register value, fixing this. The datasheet does not guarantee reliable operation above 3.3V, so on boards where this regulator is used the regulator-max-microvolt setting must be 3.3V or less. This is essentially the same as the commit f40d4896bf32 ("regulator: axp20x: Fix axp22x ldo_io registration error on cold boot") for AXP22x PMICs. Fixes: a51f9f4622a3 ("regulator: axp20x: support AXP809 variant") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/acpi/platform')