/* * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef __SOC_TEGRA_BPMP_H #define __SOC_TEGRA_BPMP_H #include #include #include #include #include struct tegra_bpmp_clk; struct tegra_bpmp_soc { struct { struct { unsigned int offset; unsigned int count; unsigned int timeout; } cpu_tx, thread, cpu_rx; } channels; unsigned int num_resets; }; struct tegra_bpmp_mb_data { u32 code; u32 flags; u8 data[MSG_DATA_MIN_SZ]; } __packed; struct tegra_bpmp_channel { struct tegra_bpmp *bpmp; struct tegra_bpmp_mb_data *ib; struct tegra_bpmp_mb_data *ob; struct completion completion; struct tegra_ivc *ivc; }; typedef void (*tegra_bpmp_mrq_handler_t)(unsigned int mrq, struct tegra_bpmp_channel *channel, void *data); struct tegra_bpmp_mrq { struct list_head list; unsigned int mrq; tegra_bpmp_mrq_handler_t handler; void *data; }; struct tegra_bpmp { const struct tegra_bpmp_soc *soc; struct device *dev; struct { struct gen_pool *pool; dma_addr_t phys; void *virt; } tx, rx; struct { struct mbox_client client; struct mbox_chan *channel; } mbox; struct tegra_bpmp_channel *channels; unsigned int num_channels; struct { unsigned long *allocated; unsigned long *busy; unsigned int count; struct semaphore lock; } threaded; struct list_head mrqs; spinlock_t lock; struct tegra_bpmp_clk **clocks; unsigned int num_clocks; struct reset_controller_dev rstc; }; struct tegra_bpmp *tegra_bpmp_get(struct device *dev); void tegra_bpmp_put(struct tegra_bpmp *bpmp); struct tegra_bpmp_message { unsigned int mrq; struct { const void *data; size_t size; } tx; struct { void *data; size_t size; } rx; }; int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp, struct tegra_bpmp_message *msg); int tegra_bpmp_transfer(struct tegra_bpmp *bpmp, struct tegra_bpmp_message *msg); int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, tegra_bpmp_mrq_handler_t handler, void *data); void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, void *data); #if IS_ENABLED(CONFIG_CLK_TEGRA_BPMP) int tegra_bpmp_init_clocks(struct tegra_bpmp *bpmp); #else static inline int tegra_bpmp_init_clocks(struct tegra_bpmp *bpmp) { return 0; } #endif #if IS_ENABLED(CONFIG_RESET_TEGRA_BPMP) int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp); #else static inline int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp) { return 0; } #endif #endif /* __SOC_TEGRA_BPMP_H */ >/rc80211_minstrel_ht.h
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authorThomas Gleixner <tglx@linutronix.de>2017-01-31 09:37:34 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-31 21:47:58 +0100
commit0becc0ae5b42828785b589f686725ff5bc3b9b25 (patch)
treebe6d0e1f37c38ed0a7dd5da2d4b1e93f0fb43101 /net/mac80211/rc80211_minstrel_ht.h
parent24c2503255d35c269b67162c397a1a1c1e02f6ce (diff)
x86/mce: Make timer handling more robust
Erik reported that on a preproduction hardware a CMCI storm triggers the BUG_ON in add_timer_on(). The reason is that the per CPU MCE timer is started by the CMCI logic before the MCE CPU hotplug callback starts the timer with add_timer_on(). So the timer is already queued which triggers the BUG. Using add_timer_on() is pretty pointless in this code because the timer is strictlty per CPU, initialized as pinned and all operations which arm the timer happen on the CPU to which the timer belongs. Simplify the whole machinery by using mod_timer() instead of add_timer_on() which avoids the problem because mod_timer() can handle already queued timers. Use __start_timer() everywhere so the earliest armed expiry time is preserved. Reported-by: Erik Veijola <erik.veijola@intel.com> Tested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@alien8.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/alpine.DEB.2.20.1701310936080.3457@nanos Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'net/mac80211/rc80211_minstrel_ht.h')