/* * drivers/video/clgenfb.h - Cirrus Logic chipset constants * * Copyright 1999 Jeff Garzik * * Original clgenfb author: Frank Neumann * * Based on retz3fb.c and clgen.c: * Copyright (C) 1997 Jes Sorensen * Copyright (C) 1996 Frank Neumann * *************************************************************** * * Format this code with GNU indent '-kr -i8 -pcs' options. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. * */ #ifndef __CLGENFB_H__ #define __CLGENFB_H__ /* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */ /* OLD COMMENT: these definitions might most of the time also work */ /* OLD COMMENT: for other CL-GD542x/543x based boards.. */ /*** External/General Registers ***/ #define CL_POS102 0x102 /* POS102 register */ #define CL_VSSM 0x46e8 /* Adapter Sleep */ #define CL_VSSM2 0x3c3 /* Motherboard Sleep */ /*** VGA Sequencer Registers ***/ /* the following are from the "extension registers" group */ #define CL_SEQR6 0x6 /* Unlock ALL Extensions */ #define CL_SEQR7 0x7 /* Extended Sequencer Mode */ #define CL_SEQR8 0x8 /* EEPROM Control */ #define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */ #define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */ #define CL_SEQRB 0xb /* VCLK0 Numerator */ #define CL_SEQRC 0xc /* VCLK1 Numerator */ #define CL_SEQRD 0xd /* VCLK2 Numerator */ #define CL_SEQRE 0xe /* VCLK3 Numerator */ #define CL_SEQRF 0xf /* DRAM Control */ #define CL_SEQR10 0x10 /* Graphics Cursor X Position */ #define CL_SEQR11 0x11 /* Graphics Cursor Y Position */ #define CL_SEQR12 0x12 /* Graphics Cursor Attributes */ #define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */ #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */ #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */ #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */ #define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */ #define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */ #define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */ #define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */ #define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */ #define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */ #define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */ #define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */ #define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */ /*** CRT Controller Registers ***/ #define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */ #define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */ #define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */ /* the following are from the "extension registers" group */ #define CL_CRT19 0x19 /* Interlace End */ #define CL_CRT1A 0x1a /* Interlace Control */ #define CL_CRT1B 0x1b /* Extended Display Controls */ #define CL_CRT1C 0x1c /* Sync adjust and genlock register */ #define CL_CRT1D 0x1d /* Overlay Extended Control register */ #define CL_CRT1E 0x1e /* Another overflow register */ #define CL_CRT25 0x25 /* Part Status Register */ #define CL_CRT27 0x27 /* ID Register */ #define CL_CRT51 0x51 /* P4 disable "flicker fixer" */ /*** Graphics Controller Registers ***/ /* the following are from the "extension registers" group */ #define CL_GR9 0x9 /* Offset Register 0 */ #define CL_GRA 0xa /* Offset Register 1 */ #define CL_GRB 0xb /* Graphics Controller Mode Extensions */ #define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */ #define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */ #define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */ #define CL_GRF 0xf /* Display Compression Control register */ #define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */ #define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */ #define CL_GR12 0x12 /* Background Color Byte 2 Register */ #define CL_GR13 0x13 /* Foreground Color Byte 2 Register */ #define CL_GR14 0x14 /* Background Color Byte 3 Register */ #define CL_GR15 0x15 /* Foreground Color Byte 3 Register */ /* the following are CL-GD5426/'28 specific blitter registers */ #define CL_GR20 0x20 /* BLT Width Low */ #define CL_GR21 0x21 /* BLT Width High */ #define CL_GR22 0x22 /* BLT Height Low */ #define CL_GR23 0x23 /* BLT Height High */ #define CL_GR24 0x24 /* BLT Destination Pitch Low */ #define CL_GR25 0x25 /* BLT Destination Pitch High */ #define CL_GR26 0x26 /* BLT Source Pitch Low */ #define CL_GR27 0x27 /* BLT Source Pitch High */ #define CL_GR28 0x28 /* BLT Destination Start Low */ #define CL_GR29 0x29 /* BLT Destination Start Mid */ #define CL_GR2A 0x2a /* BLT Destination Start High */ #define CL_GR2C 0x2c /* BLT Source Start Low */ #define CL_GR2D 0x2d /* BLT Source Start Mid */ #define CL_GR2E 0x2e /* BLT Source Start High */ #define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */ #define CL_GR30 0x30 /* BLT Mode */ #define CL_GR31 0x31 /* BLT Start/Status */ #define CL_GR32 0x32 /* BLT Raster Operation */ #define CL_GR33 0x33 /* another P4 "compat" register.. */ #define CL_GR34 0x34 /* Transparent Color Select Low */ #define CL_GR35 0x35 /* Transparent Color Select High */ #define CL_GR38 0x38 /* Source Transparent Color Mask Low */ #define CL_GR39 0x39 /* Source Transparent Color Mask High */ /*** Attribute Controller Registers ***/ #define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */ #define CL_AR34 0x34 /* TEST */ #endif /* __CLGENFB_H__ */ logplain -rw-r--r--bcm-cygnus.h3135logplain -rw-r--r--bcm-ns2.h2915logplain -rw-r--r--bcm-nsp.h2148logplain -rw-r--r--bcm21664.h1984logplain -rw-r--r--bcm281xx.h2456logplain -rw-r--r--bcm2835-aux.h635logplain -rw-r--r--bcm2835.h1962logplain -rw-r--r--berlin2.h1034logplain -rw-r--r--berlin2q.h695logplain -rw-r--r--clps711x-clock.h718logplain -rw-r--r--efm32-cmu.h1112logplain -rw-r--r--exynos-audss-clk.h597logplain -rw-r--r--exynos3250.h9083logplain -rw-r--r--exynos4.h8284logplain -rw-r--r--exynos4415.h9828logplain -rw-r--r--exynos5250.h4616logplain -rw-r--r--exynos5260-clk.h14876logplain -rw-r--r--exynos5410.h1689logplain -rw-r--r--exynos5420.h6857logplain -rw-r--r--exynos5433.h45372logplain -rw-r--r--exynos5440.h1141logplain -rw-r--r--exynos7-clk.h5281logplain -rw-r--r--gxbb-aoclkc.h2866logplain -rw-r--r--gxbb-clkc.h592logplain -rw-r--r--hi3516cv300-clock.h1668logplain -rw-r--r--hi3519-clock.h1328logplain -rw-r--r--hi3620-clock.h4496logplain -rw-r--r--hi6220-clock.h4508logplain -rw-r--r--hip04-clock.h1137logplain -rw-r--r--histb-clock.h2012logplain -rw-r--r--hix5hd2-clock.h2415logplain -rw-r--r--imx1-clock.h1055logplain -rw-r--r--imx21-clock.h2461logplain -rw-r--r--imx27-clock.h3494logplain -rw-r--r--imx5-clock.h7212logplain -rw-r--r--imx6qdl-clock.h9593logplain -rw-r--r--imx6sl-clock.h5849logplain -rw-r--r--imx6sx-clock.h9099logplain -rw-r--r--imx6ul-clock.h8203logplain -rw-r--r--imx7d-clock.h15974logplain -rw-r--r--jz4740-cgu.h1028logplain -rw-r--r--jz4780-cgu.h2470logplain -rw-r--r--lpc18xx-ccu.h2134logplain -rw-r--r--lpc18xx-cgu.h1142logplain -rw-r--r--lpc32xx-clock.h1633logplain -rw-r--r--lsi,axm5516-clks.h974logplain -rw-r--r--marvell,mmp2.h2022logplain -rw-r--r--marvell,pxa168.h1654logplain -rw-r--r--marvell,pxa1928.h1535logplain -rw-r--r--marvell,pxa910.h1598logplain -rw-r--r--maxim,max77620.h632logplain -rw-r--r--maxim,max77686.h648logplain -rw-r--r--maxim,max77802.h630logplain -rw-r--r--meson8b-clkc.h523logplain -rw-r--r--microchip,pic32-clock.h1150logplain -rw-r--r--mpc512x-clock.h2236logplain -rw-r--r--mt2701-clk.h13832logplain -rw-r--r--mt8135-clk.h5641logplain -rw-r--r--mt8173-clk.h9293logplain -rw-r--r--oxsemi,ox810se.h1002logplain -rw-r--r--oxsemi,ox820.h1203logplain -rw-r--r--pistachio-clk.h4863logplain -rw-r--r--pxa-clock.h1715logplain -rw-r--r--qcom,gcc-apq8084.h12872logplain -rw-r--r--qcom,gcc-ipq4019.h5423logplain -rw-r--r--qcom,gcc-ipq806x.h8574logplain -rw-r--r--qcom,gcc-mdm9615.h9497logplain -rw-r--r--qcom,gcc-msm8660.h7932logplain -rw-r--r--qcom,gcc-msm8916.h6190logplain -rw-r--r--qcom,gcc-msm8960.h9342logplain -rw-r--r--qcom,gcc-msm8974.h12340logplain -rw-r--r--qcom,gcc-msm8994.h4858logplain -rw-r--r--qcom,gcc-msm8996.h12575logplain -rw-r--r--qcom,lcc-ipq806x.h899logplain -rw-r--r--qcom,lcc-mdm9615.h1701logplain -rw-r--r--qcom,lcc-msm8960.h1616logplain -rw-r--r--qcom,mmcc-apq8084.h5722logplain -rw-r--r--qcom,mmcc-msm8960.h4109logplain -rw-r--r--qcom,mmcc-msm8974.h5223logplain -rw-r--r--qcom,mmcc-msm8996.h9403logplain -rw-r--r--qcom,rpmcc.h2101logplain -rw-r--r--r7s72100-clock.h1218logplain -rw-r--r--r8a73a4-clock.h1596logplain -rw-r--r--r8a7740-clock.h1992logplain -rw-r--r--r8a7743-cpg-mssr.h1269logplain -rw-r--r--r8a7745-cpg-mssr.h1298logplain -rw-r--r--r8a7778-clock.h1855logplain -rw-r--r--r8a7779-clock.h1647logplain -rw-r--r--r8a7790-clock.h4367logplain -rw-r--r--r8a7791-clock.h4388logplain -rw-r--r--r8a7792-clock.h2562logplain -rw-r--r--r8a7793-clock.h4561logplain -rw-r--r--r8a7794-clock.h3679logplain -rw-r--r--r8a7795-cpg-mssr.h1890logplain -rw-r--r--r8a7796-cpg-mssr.h2066logplain -rw-r--r--renesas-cpg-mssr.h542logplain -rw-r--r--rk1108-cru.h6605logplain -rw-r--r--rk3036-cru.h4584logplain -rw-r--r--rk3066a-cru.h1068logplain -rw-r--r--rk3188-cru-common.h6105logplain -rw-r--r--rk3188-cru.h1435logplain