/* * Copyright (C) 2009 Marvell International Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ASM_MACH_PXA168FB_H #define __ASM_MACH_PXA168FB_H #include #include /* Dumb interface */ #define PIN_MODE_DUMB_24 0 #define PIN_MODE_DUMB_18_SPI 1 #define PIN_MODE_DUMB_18_GPIO 2 #define PIN_MODE_DUMB_16_SPI 3 #define PIN_MODE_DUMB_16_GPIO 4 #define PIN_MODE_DUMB_12_SPI_GPIO 5 #define PIN_MODE_SMART_18_SPI 6 #define PIN_MODE_SMART_16_SPI 7 #define PIN_MODE_SMART_8_SPI_GPIO 8 /* Dumb interface pin allocation */ #define DUMB_MODE_RGB565 0 #define DUMB_MODE_RGB565_UPPER 1 #define DUMB_MODE_RGB666 2 #define DUMB_MODE_RGB666_UPPER 3 #define DUMB_MODE_RGB444 4 #define DUMB_MODE_RGB444_UPPER 5 #define DUMB_MODE_RGB888 6 /* default fb buffer size WVGA-32bits */ #define DEFAULT_FB_SIZE (800 * 480 * 4) /* * Buffer pixel format * bit0 is for rb swap. * bit12 is for Y UorV swap */ #define PIX_FMT_RGB565 0 #define PIX_FMT_BGR565 1 #define PIX_FMT_RGB1555 2 #define PIX_FMT_BGR1555 3 #define PIX_FMT_RGB888PACK 4 #define PIX_FMT_BGR888PACK 5 #define PIX_FMT_RGB888UNPACK 6 #define PIX_FMT_BGR888UNPACK 7 #define PIX_FMT_RGBA888 8 #define PIX_FMT_BGRA888 9 #define PIX_FMT_YUV422PACK 10 #define PIX_FMT_YVU422PACK 11 #define PIX_FMT_YUV422PLANAR 12 #define PIX_FMT_YVU422PLANAR 13 #define PIX_FMT_YUV420PLANAR 14 #define PIX_FMT_YVU420PLANAR 15 #define PIX_FMT_PSEUDOCOLOR 20 #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) /* * PXA LCD controller private state. */ struct pxa168fb_info { struct device *dev; struct clk *clk; struct fb_info *info; void __iomem *reg_base; dma_addr_t fb_start_dma; u32 pseudo_palette[16]; int pix_fmt; unsigned is_blanked:1; unsigned panel_rbswap:1; unsigned active:1; }; /* * PXA fb machine information */ struct pxa168fb_mach_info { char id[16]; int num_modes; struct fb_videomode *modes; /* * Pix_fmt */ unsigned pix_fmt; /* * I/O pin allocation. */ unsigned io_pin_allocation_mode:4; /* * Dumb panel -- assignment of R/G/B component info to the 24 * available external data lanes. */ unsigned dumb_mode:4; unsigned panel_rgb_reverse_lanes:1; /* * Dumb panel -- GPIO output data. */ unsigned gpio_output_mask:8; unsigned gpio_output_data:8; /* * Dumb panel -- configurable output signal polarity. */ unsigned invert_composite_blank:1; unsigned invert_pix_val_ena:1; unsigned invert_pixclock:1; unsigned panel_rbswap:1; unsigned active:1; unsigned enable_lcd:1; }; #endif /* __ASM_MACH_PXA168FB_H */ pe='search' size='10' name='q' value=''/>
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /include/net/udp.h
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/net/udp.h')