#ifndef __XEN_PUBLIC_XENPMU_H__ #define __XEN_PUBLIC_XENPMU_H__ #include "xen.h" #define XENPMU_VER_MAJ 0 #define XENPMU_VER_MIN 1 /* * ` enum neg_errnoval * ` HYPERVISOR_xenpmu_op(enum xenpmu_op cmd, struct xenpmu_params *args); * * @cmd == XENPMU_* (PMU operation) * @args == struct xenpmu_params */ /* ` enum xenpmu_op { */ #define XENPMU_mode_get 0 /* Also used for getting PMU version */ #define XENPMU_mode_set 1 #define XENPMU_feature_get 2 #define XENPMU_feature_set 3 #define XENPMU_init 4 #define XENPMU_finish 5 #define XENPMU_lvtpc_set 6 #define XENPMU_flush 7 /* ` } */ /* Parameters structure for HYPERVISOR_xenpmu_op call */ struct xen_pmu_params { /* IN/OUT parameters */ struct { uint32_t maj; uint32_t min; } version; uint64_t val; /* IN parameters */ uint32_t vcpu; uint32_t pad; }; /* PMU modes: * - XENPMU_MODE_OFF: No PMU virtualization * - XENPMU_MODE_SELF: Guests can profile themselves * - XENPMU_MODE_HV: Guests can profile themselves, dom0 profiles * itself and Xen * - XENPMU_MODE_ALL: Only dom0 has access to VPMU and it profiles * everyone: itself, the hypervisor and the guests. */ #define XENPMU_MODE_OFF 0 #define XENPMU_MODE_SELF (1<<0) #define XENPMU_MODE_HV (1<<1) #define XENPMU_MODE_ALL (1<<2) /* * PMU features: * - XENPMU_FEATURE_INTEL_BTS: Intel BTS support (ignored on AMD) */ #define XENPMU_FEATURE_INTEL_BTS 1 /* * Shared PMU data between hypervisor and PV(H) domains. * * The hypervisor fills out this structure during PMU interrupt and sends an * interrupt to appropriate VCPU. * Architecture-independent fields of xen_pmu_data are WO for the hypervisor * and RO for the guest but some fields in xen_pmu_arch can be writable * by both the hypervisor and the guest (see arch-$arch/pmu.h). */ struct xen_pmu_data { /* Interrupted VCPU */ uint32_t vcpu_id; /* * Physical processor on which the interrupt occurred. On non-privileged * guests set to vcpu_id; */ uint32_t pcpu_id; /* * Domain that was interrupted. On non-privileged guests set to * DOMID_SELF. * On privileged guests can be DOMID_SELF, DOMID_XEN, or, when in * XENPMU_MODE_ALL mode, domain ID of another domain. */ domid_t domain_id; uint8_t pad[6]; /* Architecture-specific information */ struct xen_pmu_arch pmu; }; #endif /* __XEN_PUBLIC_XENPMU_H__ */ ion>
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authorLinus Torvalds <torvalds@linux-foundation.org>2016-10-15 09:26:12 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2016-10-15 09:26:12 -0700
commit133d970e0dadf7b413db19893acc5b26664bf4a1 (patch)
treeea10732ca1d0f663ef1319973947a7c72cf170e7 /include/trace/events/scsi.h
parent050aaeab99067b6a08b34274ff15ca5dbb94a160 (diff)
parent38b8767462120c62a5046b529c80b06861f9ac85 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main MIPS pull request for 4.9: MIPS core arch code: - traps: 64bit kernels should read CP0_EBase 64bit - traps: Convert ebase to KSEG0 - c-r4k: Drop bc_wback_inv() from icache flush - c-r4k: Split user/kernel flush_icache_range() - cacheflush: Use __flush_icache_user_range() - uprobes: Flush icache via kernel address - KVM: Use __local_flush_icache_user_range() - c-r4k: Fix flush_icache_range() for EVA - Fix -mabi=64 build of vdso.lds - VDSO: Drop duplicated -I*/-E* aflags - tracing: move insn_has_delay_slot to a shared header - tracing: disable uprobe/kprobe on compact branch instructions - ptrace: Fix regs_return_value for kernel context - Squash lines for simple wrapper functions - Move identification of VP(E) into proc.c from smp-mt.c - Add definitions of SYNC barrierstype values - traps: Ensure full EBase is written - tlb-r4k: If there are wired entries, don't use TLBINVF - Sanitise coherentio semantics - dma-default: Don't check hw_coherentio if device is non-coherent - Support per-device DMA coherence - Adjust MIPS64 CAC_BASE to reflect Config.K0 - Support generating Flattened Image Trees (.itb) - generic: Introduce generic DT-based board support - generic: Convert SEAD-3 to a generic board - Enable hardened usercopy - Don't specify STACKPROTECTOR in defconfigs Octeon: - Delete dead code and files across the platform. - Change to use all memory into use by default. - Rename upper case variables in setup code to lowercase. - Delete legacy hack for broken bootloaders. - Leave maintaining the link state to the actual ethernet/PHY drivers. - Add DTS for D-Link DSR-500N. - Fix PCI interrupt routing on D-Link DSR-500N. Pistachio: - Remove ANDROID_TIMED_OUTPUT from defconfig TX39xx: - Move GPIO setup from .mem_setup() to .arch_init() - Convert to Common Clock Framework TX49xx: - Move GPIO setup from .mem_setup() to .arch_init() - Convert to Common Clock Framework txx9wdt: - Add missing clock (un)prepare calls for CCF BMIPS: - Add PW, GPIO SDHCI and NAND device node names - Support APPENDED_DTB - Add missing bcm97435svmb to DT_NONE - Rename bcm96358nb4ser to bcm6358-neufbox4-sercom - Add DT examples for BCM63268, BCM3368 and BCM6362 - Add support for BCM3368 and BCM6362 PCI - Reduce stack frame usage - Use struct list_head lists - Support for CONFIG_PCI_DOMAINS_GENERIC - Make pcibios_set_cache_line_size an initcall - Inline pcibios_assign_all_busses - Split pci.c into pci.c & pci-legacy.c - Introduce CONFIG_PCI_DRIVERS_LEGACY - Support generic drivers CPC - Convert bare 'unsigned' to 'unsigned int' - Avoid lock when MIPS CM >= 3 is present GIC: - Delete unused file smp-gic.c mt7620: - Delete unnecessary assignment for the field "owner" from PCI BCM63xx: - Let clk_disable() return immediately if clk is NULL pm-cps: - Change FSB workaround to CPU blacklist - Update comments on barrier instructions - Use MIPS standard lightweight ordering barrier - Use MIPS standard completion barrier - Remove selection of sync types - Add MIPSr6 CPU support - Support CM3 changes to Coherence Enable Register SMP: - Wrap call to mips_cpc_lock_other in mips_cm_lock_other - Introduce mechanism for freeing and allocating IPIs cpuidle: - cpuidle-cps: Enable use with MIPSr6 CPUs. SEAD3: - Rewrite to use DT and generic kernel feature. USB: - host: ehci-sead3: Remove SEAD-3 EHCI code FBDEV: - cobalt_lcdfb: Drop SEAD3 support dt-bindings: - Document a binding for simple ASCII LCDs auxdisplay: - img-ascii-lcd: driver for simple ASCII LCD displays irqchip i8259: - i8259: Add domain before mapping parent irq - i8259: Allow platforms to override poll function - i8259: Remove unused i8259A_irq_pending Malta: - Rewrite to use DT of/platform: - Probe "isa" busses by default CM: - Print CM error reports upon bus errors Module: - Migrate exception table users off module.h and onto extable.h - Make various drivers explicitly non-modular: - Audit and remove any unnecessary uses of module.h mailmap: - Canonicalize to Qais' current email address. Documentation: - MIPS supports HAVE_REGS_AND_STACK_ACCESS_API Loongson1C: - Add CPU support for Loongson1C - Add board support - Add defconfig - Add RTC support for Loongson1C board All this except one Documentation fix has sat in linux-next and has survived Imagination's automated build test system" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (127 commits) Documentation: MIPS supports HAVE_REGS_AND_STACK_ACCESS_API MIPS: ptrace: Fix regs_return_value for kernel context MIPS: VDSO: Drop duplicated -I*/-E* aflags MIPS: Fix -mabi=64 build of vdso.lds MIPS: Enable hardened usercopy MIPS: generic: Convert SEAD-3 to a generic board MIPS: generic: Introduce generic DT-based board support MIPS: Support generating Flattened Image Trees (.itb) MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0 MIPS: Print CM error reports upon bus errors MIPS: Support per-device DMA coherence MIPS: dma-default: Don't check hw_coherentio if device is non-coherent MIPS: Sanitise coherentio semantics MIPS: PCI: Support generic drivers MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY MIPS: PCI: Split pci.c into pci.c & pci-legacy.c MIPS: PCI: Inline pcibios_assign_all_busses MIPS: PCI: Make pcibios_set_cache_line_size an initcall MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC MIPS: PCI: Use struct list_head lists ...
Diffstat (limited to 'include/trace/events/scsi.h')