/* * DDR addressing details and AC timing parameters from JEDEC specs * * Copyright (C) 2012 Texas Instruments, Inc. * * Aneesh V * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include /* LPDDR2 addressing details from JESD209-2 section 2.4 */ const struct lpddr2_addressing lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = { {B4, T_REFI_15_6, T_RFC_90}, /* 64M */ {B4, T_REFI_15_6, T_RFC_90}, /* 128M */ {B4, T_REFI_7_8, T_RFC_90}, /* 256M */ {B4, T_REFI_7_8, T_RFC_90}, /* 512M */ {B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */ {B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */ {B8, T_REFI_3_9, T_RFC_130}, /* 4G */ {B8, T_REFI_3_9, T_RFC_210}, /* 8G */ {B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */ {B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */ }; EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table); /* LPDDR2 AC timing parameters from JESD209-2 section 12 */ const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = { /* Speed bin 400(200 MHz) */ [0] = { .max_freq = 200000000, .min_freq = 10000000, .tRPab = 21000, .tRCD = 18000, .tWR = 15000, .tRAS_min = 42000, .tRRD = 10000, .tWTR = 10000, .tXP = 7500, .tRTP = 7500, .tCKESR = 15000, .tDQSCK_max = 5500, .tFAW = 50000, .tZQCS = 90000, .tZQCL = 360000, .tZQinit = 1000000, .tRAS_max_ns = 70000, .tDQSCK_max_derated = 6000, }, /* Speed bin 533(266 MHz) */ [1] = { .max_freq = 266666666, .min_freq = 10000000, .tRPab = 21000, .tRCD = 18000, .tWR = 15000, .tRAS_min = 42000, .tRRD = 10000, .tWTR = 7500, .tXP = 7500, .tRTP = 7500, .tCKESR = 15000, .tDQSCK_max = 5500, .tFAW = 50000, .tZQCS = 90000, .tZQCL = 360000, .tZQinit = 1000000, .tRAS_max_ns = 70000, .tDQSCK_max_derated = 6000, }, /* Speed bin 800(400 MHz) */ [2] = { .max_freq = 400000000, .min_freq = 10000000, .tRPab = 21000, .tRCD = 18000, .tWR = 15000, .tRAS_min = 42000, .tRRD = 10000, .tWTR = 7500, .tXP = 7500, .tRTP = 7500, .tCKESR = 15000, .tDQSCK_max = 5500, .tFAW = 50000, .tZQCS = 90000, .tZQCL = 360000, .tZQinit = 1000000, .tRAS_max_ns = 70000, .tDQSCK_max_derated = 6000, }, /* Speed bin 1066(533 MHz) */ [3] = { .max_freq = 533333333, .min_freq = 10000000, .tRPab = 21000, .tRCD = 18000, .tWR = 15000, .tRAS_min = 42000, .tRRD = 10000, .tWTR = 7500, .tXP = 7500, .tRTP = 7500, .tCKESR = 15000, .tDQSCK_max = 5500, .tFAW = 50000, .tZQCS = 90000, .tZQCL = 360000, .tZQinit = 1000000, .tRAS_max_ns = 70000, .tDQSCK_max_derated = 5620, }, }; EXPORT_SYMBOL_GPL(lpddr2_jedec_timings); const struct lpddr2_min_tck lpddr2_jedec_min_tck = { .tRPab = 3, .tRCD = 3, .tWR = 3, .tRASmin = 3, .tRRD = 2, .tWTR = 2, .tXP = 2, .tRTP = 2, .tCKE = 3, .tCKESR = 3, .tFAW = 8 }; EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck); include/uapi/sound?id=04d8a0a5f3b6887543850d991a5e37c4ec90e250'>sound/usb_stream.h
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authorRaju Lakkaraju <Raju.Lakkaraju@microsemi.com>2017-02-07 19:10:26 +0530
committerDavid S. Miller <davem@davemloft.net>2017-02-08 13:29:04 -0500
commit04d8a0a5f3b6887543850d991a5e37c4ec90e250 (patch)
treeee1fafb2122c2b29c7cb19e571bd7229afdbf847 /include/uapi/sound/usb_stream.h
parentff4cf0e5ce952488074aa7f47734af1794f55fbc (diff)
net: phy: Add LED mode driver for Microsemi PHYs.
LED Mode: Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different status information that can be selected by setting LED mode. LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get from Device Tree. Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/uapi/sound/usb_stream.h')