/* ----------------------------------------------------------------------- * * neon.uc - RAID-6 syndrome calculation using ARM NEON instructions * * Copyright (C) 2012 Rob Herring * Copyright (C) 2015 Linaro Ltd. * * Based on altivec.uc: * Copyright 2002-2004 H. Peter Anvin - All Rights Reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, Inc., 53 Temple Place Ste 330, * Boston MA 02111-1307, USA; either version 2 of the License, or * (at your option) any later version; incorporated herein by reference. * * ----------------------------------------------------------------------- */ /* * neon$#.c * * $#-way unrolled NEON intrinsics math RAID-6 instruction set * * This file is postprocessed using unroll.awk */ #include typedef uint8x16_t unative_t; #define NBYTES(x) ((unative_t){x,x,x,x, x,x,x,x, x,x,x,x, x,x,x,x}) #define NSIZE sizeof(unative_t) /* * The SHLBYTE() operation shifts each byte left by 1, *not* * rolling over into the next byte */ static inline unative_t SHLBYTE(unative_t v) { return vshlq_n_u8(v, 1); } /* * The MASK() operation returns 0xFF in any byte for which the high * bit is 1, 0x00 for any byte for which the high bit is 0. */ static inline unative_t MASK(unative_t v) { const uint8x16_t temp = NBYTES(0); return (unative_t)vcltq_s8((int8x16_t)v, (int8x16_t)temp); } void raid6_neon$#_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs) { uint8_t **dptr = (uint8_t **)ptrs; uint8_t *p, *q; int d, z, z0; register unative_t wd$$, wq$$, wp$$, w1$$, w2$$; const unative_t x1d = NBYTES(0x1d); z0 = disks - 3; /* Highest data disk */ p = dptr[z0+1]; /* XOR parity */ q = dptr[z0+2]; /* RS syndrome */ for ( d = 0 ; d < bytes ; d += NSIZE*$# ) { wq$$ = wp$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]); for ( z = z0-1 ; z >= 0 ; z-- ) { wd$$ = vld1q_u8(&dptr[z][d+$$*NSIZE]); wp$$ = veorq_u8(wp$$, wd$$); w2$$ = MASK(wq$$); w1$$ = SHLBYTE(wq$$); w2$$ = vandq_u8(w2$$, x1d); w1$$ = veorq_u8(w1$$, w2$$); wq$$ = veorq_u8(w1$$, wd$$); } vst1q_u8(&p[d+NSIZE*$$], wp$$); vst1q_u8(&q[d+NSIZE*$$], wq$$); } } void raid6_neon$#_xor_syndrome_real(int disks, int start, int stop, unsigned long bytes, void **ptrs) { uint8_t **dptr = (uint8_t **)ptrs; uint8_t *p, *q; int d, z, z0; register unative_t wd$$, wq$$, wp$$, w1$$, w2$$; const unative_t x1d = NBYTES(0x1d); z0 = stop; /* P/Q right side optimization */ p = dptr[disks-2]; /* XOR parity */ q = dptr[disks-1]; /* RS syndrome */ for ( d = 0 ; d < bytes ; d += NSIZE*$# ) { wq$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]); wp$$ = veorq_u8(vld1q_u8(&p[d+$$*NSIZE]), wq$$); /* P/Q data pages */ for ( z = z0-1 ; z >= start ; z-- ) { wd$$ = vld1q_u8(&dptr[z][d+$$*NSIZE]); wp$$ = veorq_u8(wp$$, wd$$); w2$$ = MASK(wq$$); w1$$ = SHLBYTE(wq$$); w2$$ = vandq_u8(w2$$, x1d); w1$$ = veorq_u8(w1$$, w2$$); wq$$ = veorq_u8(w1$$, wd$$); } /* P/Q left side optimization */ for ( z = start-1 ; z >= 0 ; z-- ) { w2$$ = MASK(wq$$); w1$$ = SHLBYTE(wq$$); w2$$ = vandq_u8(w2$$, x1d); wq$$ = veorq_u8(w1$$, w2$$); } w1$$ = vld1q_u8(&q[d+NSIZE*$$]); wq$$ = veorq_u8(wq$$, w1$$); vst1q_u8(&p[d+NSIZE*$$], wp$$); vst1q_u8(&q[d+NSIZE*$$], wq$$); } } cted'>3space:mode:
authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /include/net/9p
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'include/net/9p')