/* * Copyright (C) ST-Ericsson AB 2010 * Author: Sjur Brendeland * License terms: GNU General Public License (GPL) version 2 */ #define pr_fmt(fmt) KBUILD_MODNAME ":%s(): " fmt, __func__ #include #include #include #include #include #include #include #define container_obj(layr) ((struct cfsrvl *) layr) static int cfvidl_receive(struct cflayer *layr, struct cfpkt *pkt); static int cfvidl_transmit(struct cflayer *layr, struct cfpkt *pkt); struct cflayer *cfvidl_create(u8 channel_id, struct dev_info *dev_info) { struct cfsrvl *vid = kzalloc(sizeof(struct cfsrvl), GFP_ATOMIC); if (!vid) return NULL; caif_assert(offsetof(struct cfsrvl, layer) == 0); cfsrvl_init(vid, channel_id, dev_info, false); vid->layer.receive = cfvidl_receive; vid->layer.transmit = cfvidl_transmit; snprintf(vid->layer.name, CAIF_LAYER_NAME_SZ - 1, "vid1"); return &vid->layer; } static int cfvidl_receive(struct cflayer *layr, struct cfpkt *pkt) { u32 videoheader; if (cfpkt_extr_head(pkt, &videoheader, 4) < 0) { pr_err("Packet is erroneous!\n"); cfpkt_destroy(pkt); return -EPROTO; } return layr->up->receive(layr->up, pkt); } static int cfvidl_transmit(struct cflayer *layr, struct cfpkt *pkt) { struct cfsrvl *service = container_obj(layr); struct caif_payload_info *info; u32 videoheader = 0; int ret; if (!cfsrvl_ready(service, &ret)) { cfpkt_destroy(pkt); return ret; } cfpkt_add_head(pkt, &videoheader, 4); /* Add info for MUX-layer to route the packet out */ info = cfpkt_info(pkt); info->channel_id = service->layer.id; info->dev_info = &service->dev_info; return layr->dn->transmit(layr->dn, pkt); } 383d0fca7035a12f1201277d33e8fc87c9d60c9a'>treecommitdiff
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authorVenkat Reddy Talla <vreddytalla@nvidia.com>2016-11-17 23:24:35 +0530
committerMark Brown <broonie@kernel.org>2016-11-23 16:27:24 +0000
commit383d0fca7035a12f1201277d33e8fc87c9d60c9a (patch)
treebb12c78d91ab8d69ae18fbbf4033277481b277ad /net/tipc
parent9a40cb0cb8b55ecfdcd3cec1381bcc46ec488588 (diff)
regulator: max77620: add support to configure MPOK
Adding support to configure regulator POK mapping bit to control nRST_IO and GPIO1 POK function. In tegra based platform which uses MAX20024 pmic, when some of regulators are configured FPS_NONE(flexible power sequencer) causes PMIC GPIO1 to go low which lead to various other rails turning off, to avoid this MPOK bit of those regulators need to be set to 0 so that PMIC GPIO1 will not go low. Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'net/tipc')