/* * Apple Onboard Audio driver for tas codec (header) * * Copyright 2006 Johannes Berg * * GPL v2, can be found in COPYING. */ #ifndef __SND_AOA_CODECTASH #define __SND_AOA_CODECTASH #define TAS_REG_MCS 0x01 /* main control */ # define TAS_MCS_FASTLOAD (1<<7) # define TAS_MCS_SCLK64 (1<<6) # define TAS_MCS_SPORT_MODE_MASK (3<<4) # define TAS_MCS_SPORT_MODE_I2S (2<<4) # define TAS_MCS_SPORT_MODE_RJ (1<<4) # define TAS_MCS_SPORT_MODE_LJ (0<<4) # define TAS_MCS_SPORT_WL_MASK (3<<0) # define TAS_MCS_SPORT_WL_16BIT (0<<0) # define TAS_MCS_SPORT_WL_18BIT (1<<0) # define TAS_MCS_SPORT_WL_20BIT (2<<0) # define TAS_MCS_SPORT_WL_24BIT (3<<0) #define TAS_REG_DRC 0x02 #define TAS_REG_VOL 0x04 #define TAS_REG_TREBLE 0x05 #define TAS_REG_BASS 0x06 #define TAS_REG_LMIX 0x07 #define TAS_REG_RMIX 0x08 #define TAS_REG_ACR 0x40 /* analog control */ # define TAS_ACR_B_MONAUREAL (1<<7) # define TAS_ACR_B_MON_SEL_RIGHT (1<<6) # define TAS_ACR_DEEMPH_MASK (3<<2) # define TAS_ACR_DEEMPH_OFF (0<<2) # define TAS_ACR_DEEMPH_48KHz (1<<2) # define TAS_ACR_DEEMPH_44KHz (2<<2) # define TAS_ACR_INPUT_B (1<<1) # define TAS_ACR_ANALOG_PDOWN (1<<0) #define TAS_REG_MCS2 0x43 /* main control 2 */ # define TAS_MCS2_ALLPASS (1<<1) #define TAS_REG_LEFT_BIQUAD6 0x10 #define TAS_REG_RIGHT_BIQUAD6 0x19 #define TAS_REG_LEFT_LOUDNESS 0x21 #define TAS_REG_RIGHT_LOUDNESS 0x22 #define TAS_REG_LEFT_LOUDNESS_GAIN 0x23 #define TAS_REG_RIGHT_LOUDNESS_GAIN 0x24 #define TAS3001_DRC_MAX 0x5f #define TAS3004_DRC_MAX 0xef #endif /* __SND_AOA_CODECTASH */ -private-remove'>summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAlex <alex.g@adaptrum.com>2016-12-06 10:56:51 -0800
committerDavid S. Miller <davem@davemloft.net>2016-12-07 13:12:17 -0500
commit74685b08fbb26ff5b8448fabe0941a53269dd33e (patch)
tree10715d3af4ad86f119a32cc4b47780b8b5ca5ee5
parent233900d8857dc426557751e30b2150778974417c (diff)
drivers: net: cpsw-phy-sel: Clear RGMII_IDMODE on "rgmii" links
Support for setting the RGMII_IDMODE bit was added in the commit referenced below. However, that commit did not add the symmetrical clearing of the bit by way of setting it in "mask". Add it here. Note that the documentation marks clearing this bit as "reserved", however, according to TI, support for delaying the clock does exist in the MAC, although it is not officially supported. We tested this on a board with an RGMII to RGMII link that will not work unless this bit is cleared. Fixes: 0fb26c3063ea ("drivers: net: cpsw-phy-sel: add support to configure rgmii internal delay") Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat