/* * Apple Onboard Audio driver for tas codec (header) * * Copyright 2006 Johannes Berg * * GPL v2, can be found in COPYING. */ #ifndef __SND_AOA_CODECTASH #define __SND_AOA_CODECTASH #define TAS_REG_MCS 0x01 /* main control */ # define TAS_MCS_FASTLOAD (1<<7) # define TAS_MCS_SCLK64 (1<<6) # define TAS_MCS_SPORT_MODE_MASK (3<<4) # define TAS_MCS_SPORT_MODE_I2S (2<<4) # define TAS_MCS_SPORT_MODE_RJ (1<<4) # define TAS_MCS_SPORT_MODE_LJ (0<<4) # define TAS_MCS_SPORT_WL_MASK (3<<0) # define TAS_MCS_SPORT_WL_16BIT (0<<0) # define TAS_MCS_SPORT_WL_18BIT (1<<0) # define TAS_MCS_SPORT_WL_20BIT (2<<0) # define TAS_MCS_SPORT_WL_24BIT (3<<0) #define TAS_REG_DRC 0x02 #define TAS_REG_VOL 0x04 #define TAS_REG_TREBLE 0x05 #define TAS_REG_BASS 0x06 #define TAS_REG_LMIX 0x07 #define TAS_REG_RMIX 0x08 #define TAS_REG_ACR 0x40 /* analog control */ # define TAS_ACR_B_MONAUREAL (1<<7) # define TAS_ACR_B_MON_SEL_RIGHT (1<<6) # define TAS_ACR_DEEMPH_MASK (3<<2) # define TAS_ACR_DEEMPH_OFF (0<<2) # define TAS_ACR_DEEMPH_48KHz (1<<2) # define TAS_ACR_DEEMPH_44KHz (2<<2) # define TAS_ACR_INPUT_B (1<<1) # define TAS_ACR_ANALOG_PDOWN (1<<0) #define TAS_REG_MCS2 0x43 /* main control 2 */ # define TAS_MCS2_ALLPASS (1<<1) #define TAS_REG_LEFT_BIQUAD6 0x10 #define TAS_REG_RIGHT_BIQUAD6 0x19 #define TAS_REG_LEFT_LOUDNESS 0x21 #define TAS_REG_RIGHT_LOUDNESS 0x22 #define TAS_REG_LEFT_LOUDNESS_GAIN 0x23 #define TAS_REG_RIGHT_LOUDNESS_GAIN 0x24 #define TAS3001_DRC_MAX 0x5f #define TAS3004_DRC_MAX 0xef #endif /* __SND_AOA_CODECTASH */ .cgi/linux/net-next.git/'>summaryrefslogtreecommitdiff
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /net/dccp/ccids/ccid2.h
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'net/dccp/ccids/ccid2.h')