/* * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c * which contain: * * Author: Nicolas Pitre * Created: Dec 02, 2004 * Copyright: MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include static DEFINE_MUTEX(car_mutex); static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); static volatile long gsr_bits; static struct clk *ac97_clk; static struct clk *ac97conf_clk; static int reset_gpio; extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio); /* * Beware PXA27x bugs: * * o Slot 12 read from modem space will hang controller. * o CDONE, SDONE interrupt fails after any slot 12 IO. * * We therefore have an hybrid approach for waiting on SDONE (interrupt or * 1 jiffy timeout if interrupt never comes). */ unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { unsigned short val = -1; volatile u32 *reg_addr; mutex_lock(&car_mutex); /* set up primary or secondary codec space */ if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; else reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; reg_addr += (reg >> 1); /* start read access across the ac97 link */ GSR = GSR_CDONE | GSR_SDONE; gsr_bits = 0; val = *reg_addr; if (reg == AC97_GPIO_STATUS) goto out; if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 && !((GSR | gsr_bits) & GSR_SDONE)) { printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n", __func__, reg, GSR | gsr_bits); val = -1; goto out; } /* valid data now */ GSR = GSR_CDONE | GSR_SDONE; gsr_bits = 0; val = *reg_addr; /* but we've just started another cycle... */ wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); out: mutex_unlock(&car_mutex); return val; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_read); void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { volatile u32 *reg_addr; mutex_lock(&car_mutex); /* set up primary or secondary codec space */ if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; else reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; reg_addr += (reg >> 1); GSR = GSR_CDONE | GSR_SDONE; gsr_bits = 0; *reg_addr = val; if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 && !((GSR | gsr_bits) & GSR_CDONE)) printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n", __func__, reg, GSR | gsr_bits); mutex_unlock(&car_mutex); } EXPORT_SYMBOL_GPL(pxa2xx_ac97_write); #ifdef CONFIG_PXA25x static inline void pxa_ac97_warm_pxa25x(void) { gsr_bits = 0; GCR |= GCR_WARM_RST; } static inline void pxa_ac97_cold_pxa25x(void) { GCR &= GCR_COLD_RST; /* clear everything but nCRST */ GCR &= ~GCR_COLD_RST; /* then assert nCRST */ gsr_bits = 0; GCR = GCR_COLD_RST; } #endif #ifdef CONFIG_PXA27x static inline void pxa_ac97_warm_pxa27x(void) { gsr_bits = 0; /* warm reset broken on Bulverde, so manually keep AC97 reset high */ pxa27x_configure_ac97reset(reset_gpio, true); udelay(10); GCR |= GCR_WARM_RST; pxa27x_configure_ac97reset(reset_gpio, false); udelay(500); } static inline void pxa_ac97_cold_pxa27x(void) { GCR &= GCR_COLD_RST; /* clear everything but nCRST */ GCR &= ~GCR_COLD_RST; /* then assert nCRST */ gsr_bits = 0; /* PXA27x Developers Manual section 13.5.2.2.1 */ clk_prepare_enable(ac97conf_clk); udelay(5); clk_disable_unprepare(ac97conf_clk); GCR = GCR_COLD_RST | GCR_WARM_RST; } #endif #ifdef CONFIG_PXA3xx static inline void pxa_ac97_warm_pxa3xx(void) { gsr_bits = 0; /* Can't use interrupts */ GCR |= GCR_WARM_RST; } static inline void pxa_ac97_cold_pxa3xx(void) { /* Hold CLKBPB for 100us */ GCR = 0; GCR = GCR_CLKBPB; udelay(100); GCR = 0; GCR &= GCR_COLD_RST; /* clear everything but nCRST */ GCR &= ~GCR_COLD_RST; /* then assert nCRST */ gsr_bits = 0; /* Can't use interrupts on PXA3xx */ GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); GCR = GCR_WARM_RST | GCR_COLD_RST; } #endif bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97) { unsigned long gsr; unsigned int timeout = 100; #ifdef CONFIG_PXA25x if (cpu_is_pxa25x()) pxa_ac97_warm_pxa25x(); else #endif #ifdef CONFIG_PXA27x if (cpu_is_pxa27x()) pxa_ac97_warm_pxa27x(); else #endif #ifdef CONFIG_PXA3xx if (cpu_is_pxa3xx()) pxa_ac97_warm_pxa3xx(); else #endif snd_BUG(); while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) mdelay(1); gsr = GSR | gsr_bits; if (!(gsr & (GSR_PCR | GSR_SCR))) { printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", __func__, gsr); return false; } return true; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset); bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97) { unsigned long gsr; unsigned int timeout = 1000; #ifdef CONFIG_PXA25x if (cpu_is_pxa25x()) pxa_ac97_cold_pxa25x(); else #endif #ifdef CONFIG_PXA27x if (cpu_is_pxa27x()) pxa_ac97_cold_pxa27x(); else #endif #ifdef CONFIG_PXA3xx if (cpu_is_pxa3xx()) pxa_ac97_cold_pxa3xx(); else #endif snd_BUG(); while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) mdelay(1); gsr = GSR | gsr_bits; if (!(gsr & (GSR_PCR | GSR_SCR))) { printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", __func__, gsr); return false; } return true; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset); void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97) { GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); GCR |= GCR_SDONE_IE|GCR_CDONE_IE; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset); static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) { long status; status = GSR; if (status) { GSR = status; gsr_bits |= status; wake_up(&gsr_wq); /* Although we don't use those we still need to clear them since they tend to spuriously trigger when MMC is used (hardware bug? go figure)... */ if (cpu_is_pxa27x()) { MISR = MISR_EOC; PISR = PISR_EOC; MCSR = MCSR_EOC; } return IRQ_HANDLED; } return IRQ_NONE; } #ifdef CONFIG_PM int pxa2xx_ac97_hw_suspend(void) { GCR |= GCR_ACLINK_OFF; clk_disable_unprepare(ac97_clk); return 0; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend); int pxa2xx_ac97_hw_resume(void) { clk_prepare_enable(ac97_clk); return 0; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume); #endif int pxa2xx_ac97_hw_probe(struct platform_device *dev) { int ret; pxa2xx_audio_ops_t *pdata = dev->dev.platform_data; if (pdata) { switch (pdata->reset_gpio) { case 95: case 113: reset_gpio = pdata->reset_gpio; break; case 0: reset_gpio = 113; break; case -1: break; default: dev_err(&dev->dev, "Invalid reset GPIO %d\n", pdata->reset_gpio); } } else { if (cpu_is_pxa27x()) reset_gpio = 113; } if (cpu_is_pxa27x()) { /* * This gpio is needed for a work-around to a bug in the ac97 * controller during warm reset. The direction and level is set * here so that it is an output driven high when switching from * AC97_nRESET alt function to generic gpio. */ ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH, "pxa27x ac97 reset"); if (ret < 0) { pr_err("%s: gpio_request_one() failed: %d\n", __func__, ret); goto err_conf; } pxa27x_configure_ac97reset(reset_gpio, false); ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); if (IS_ERR(ac97conf_clk)) { ret = PTR_ERR(ac97conf_clk); ac97conf_clk = NULL; goto err_conf; } } ac97_clk = clk_get(&dev->dev, "AC97CLK"); if (IS_ERR(ac97_clk)) { ret = PTR_ERR(ac97_clk); ac97_clk = NULL; goto err_clk; } ret = clk_prepare_enable(ac97_clk); if (ret) goto err_clk2; ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL); if (ret < 0) goto err_irq; return 0; err_irq: GCR |= GCR_ACLINK_OFF; err_clk2: clk_put(ac97_clk); ac97_clk = NULL; err_clk: if (ac97conf_clk) { clk_put(ac97conf_clk); ac97conf_clk = NULL; } err_conf: return ret; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe); void pxa2xx_ac97_hw_remove(struct platform_device *dev) { if (cpu_is_pxa27x()) gpio_free(reset_gpio); GCR |= GCR_ACLINK_OFF; free_irq(IRQ_AC97, NULL); if (ac97conf_clk) { clk_put(ac97conf_clk); ac97conf_clk = NULL; } clk_disable_unprepare(ac97_clk); clk_put(ac97_clk); ac97_clk = NULL; } EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove); MODULE_AUTHOR("Nicolas Pitre"); MODULE_DESCRIPTION("Intel/Marvell PXA sound library"); MODULE_LICENSE("GPL"); code is setting the buf to NULL to annotate an abort has occurred. Replace this mechanism by simply using the state check instead. All the other code in place already uses similar checks for aborting as well so no further changes are needed. An oops can be reproduced with the new fw_fallback.sh fallback mechanism cancellation test. Either cancelling the fallback mechanism or the custom fallback mechanism triggers a crash. mcgrof@piggy ~/linux-next/tools/testing/selftests/firmware (git::20170111-fw-fixes)$ sudo ./fw_fallback.sh ./fw_fallback.sh: timeout works ./fw_fallback.sh: firmware comparison works ./fw_fallback.sh: fallback mechanism works [ this then sits here when it is trying the cancellation test ] Kernel log: test_firmware: loading 'nope-test-firmware.bin' misc test_firmware: Direct firmware load for nope-test-firmware.bin failed with error -2 misc test_firmware: Falling back to user helper BUG: unable to handle kernel NULL pointer dereference at 0000000000000038 IP: _request_firmware+0xa27/0xad0 PGD 0 Oops: 0000 [#1] SMP Modules linked in: test_firmware(E) ... etc ... CPU: 1 PID: 1396 Comm: fw_fallback.sh Tainted: G W E 4.10.0-rc3-next-20170111+ #30 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.10.1-0-g8891697-prebuilt.qemu-project.org 04/01/2014 task: ffff9740b27f4340 task.stack: ffffbb15c0bc8000 RIP: 0010:_request_firmware+0xa27/0xad0 RSP: 0018:ffffbb15c0bcbd10 EFLAGS: 00010246 RAX: 00000000fffffffe RBX: ffff9740afe5aa80 RCX: 0000000000000000 RDX: ffff9740b27f4340 RSI: 0000000000000283 RDI: 0000000000000000 RBP: ffffbb15c0bcbd90 R08: ffffbb15c0bcbcd8 R09: 0000000000000000 R10: 0000000894a0d4b1 R11: 000000000000008c R12: ffffffffc0312480 R13: 0000000000000005 R14: ffff9740b1c32400 R15: 00000000000003e8 FS: 00007f8604422700(0000) GS:ffff9740bfc80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000038 CR3: 000000012164c000 CR4: 00000000000006e0 Call Trace: request_firmware+0x37/0x50 trigger_request_store+0x79/0xd0 [test_firmware] dev_attr_store+0x18/0x30 sysfs_kf_write+0x37/0x40 kernfs_fop_write+0x110/0x1a0 __vfs_write+0x37/0x160 ? _cond_resched+0x1a/0x50 vfs_write+0xb5/0x1a0 SyS_write+0x55/0xc0 ? trace_do_page_fault+0x37/0xd0 entry_SYSCALL_64_fastpath+0x1e/0xad RIP: 0033:0x7f8603f49620 RSP: 002b:00007fff6287b788 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 RAX: ffffffffffffffda RBX: 000055c307b110a0 RCX: 00007f8603f49620 RDX: 0000000000000016 RSI: 000055c3084d8a90 RDI: 0000000000000001 RBP: 0000000000000016 R08: 000000000000c0ff R09: 000055c3084d6336 R10: 000055c307b108b0 R11: 0000000000000246 R12: 000055c307b13c80 R13: 000055c3084d6320 R14: 0000000000000000 R15: 00007fff6287b950 Code: 9f 64 84 e8 9c 61 fe ff b8 f4 ff ff ff e9 6b f9 ff ff 48 c7 c7 40 6b 8d 84 89 45 a8 e8 43 84 18 00 49 8b be 00 03 00 00 8b 45 a8 <83> 7f 38 02 74 08 e8 6e ec ff ff 8b 45 a8 49 c7 86 00 03 00 00 RIP: _request_firmware+0xa27/0xad0 RSP: ffffbb15c0bcbd10 CR2: 0000000000000038 ---[ end trace 6d94ac339c133e6f ]--- Fixes: 5d47ec02c37e ("firmware: Correct handling of fw_state_wait() return value") Reported-and-Tested-by: Jakub Kicinski <jakub.kicinski@netronome.com> Reported-and-Tested-by: Patrick Bruenn <p.bruenn@beckhoff.com> Reported-by: Chris Wilson <chris@chris-wilson.co.uk> CC: <stable@vger.kernel.org> [3.10+] Signed-off-by: Luis R. Rodriguez <mcgrof@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'sound/soc/codecs/adau1701.h')