/* * dice.h - a part of driver for Dice based devices * * Copyright (c) Clemens Ladisch * Copyright (c) 2014 Takashi Sakamoto * * Licensed under the terms of the GNU General Public License, version 2. */ #ifndef SOUND_DICE_H_INCLUDED #define SOUND_DICE_H_INCLUDED #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../amdtp-am824.h" #include "../iso-resources.h" #include "../lib.h" #include "dice-interface.h" /* * This module support maximum 2 pairs of tx/rx isochronous streams for * our convinience. * * In documents for ASICs called with a name of 'DICE': * - ASIC for DICE II: * - Maximum 2 tx and 4 rx are supported. * - A packet supports maximum 16 data channels. * - TCD2210/2210-E (so-called 'Dice Mini'): * - Maximum 2 tx and 2 rx are supported. * - A packet supports maximum 16 data channels. * - TCD2220/2220-E (so-called 'Dice Jr.') * - 2 tx and 2 rx are supported. * - A packet supports maximum 16 data channels. * - TCD3070-CH (so-called 'Dice III') * - Maximum 2 tx and 2 rx are supported. * - A packet supports maximum 32 data channels. * * For the above, MIDI conformant data channel is just on the first isochronous * stream. */ #define MAX_STREAMS 2 struct snd_dice { struct snd_card *card; struct fw_unit *unit; spinlock_t lock; struct mutex mutex; bool registered; struct delayed_work dwork; /* Offsets for sub-addresses */ unsigned int global_offset; unsigned int rx_offset; unsigned int tx_offset; unsigned int sync_offset; unsigned int rsrv_offset; unsigned int clock_caps; struct fw_address_handler notification_handler; int owner_generation; u32 notification_bits; /* For uapi */ int dev_lock_count; /* > 0 driver, < 0 userspace */ bool dev_lock_changed; wait_queue_head_t hwdep_wait; /* For streaming */ struct fw_iso_resources tx_resources[MAX_STREAMS]; struct fw_iso_resources rx_resources[MAX_STREAMS]; struct amdtp_stream tx_stream[MAX_STREAMS]; struct amdtp_stream rx_stream[MAX_STREAMS]; bool global_enabled; struct completion clock_accepted; unsigned int substreams_counter; bool force_two_pcms; }; enum snd_dice_addr_type { SND_DICE_ADDR_TYPE_PRIVATE, SND_DICE_ADDR_TYPE_GLOBAL, SND_DICE_ADDR_TYPE_TX, SND_DICE_ADDR_TYPE_RX, SND_DICE_ADDR_TYPE_SYNC, SND_DICE_ADDR_TYPE_RSRV, }; int snd_dice_transaction_write(struct snd_dice *dice, enum snd_dice_addr_type type, unsigned int offset, void *buf, unsigned int len); int snd_dice_transaction_read(struct snd_dice *dice, enum snd_dice_addr_type type, unsigned int offset, void *buf, unsigned int len); static inline int snd_dice_transaction_write_global(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_write(dice, SND_DICE_ADDR_TYPE_GLOBAL, offset, buf, len); } static inline int snd_dice_transaction_read_global(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_read(dice, SND_DICE_ADDR_TYPE_GLOBAL, offset, buf, len); } static inline int snd_dice_transaction_write_tx(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_write(dice, SND_DICE_ADDR_TYPE_TX, offset, buf, len); } static inline int snd_dice_transaction_read_tx(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_read(dice, SND_DICE_ADDR_TYPE_TX, offset, buf, len); } static inline int snd_dice_transaction_write_rx(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_write(dice, SND_DICE_ADDR_TYPE_RX, offset, buf, len); } static inline int snd_dice_transaction_read_rx(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_read(dice, SND_DICE_ADDR_TYPE_RX, offset, buf, len); } static inline int snd_dice_transaction_write_sync(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_write(dice, SND_DICE_ADDR_TYPE_SYNC, offset, buf, len); } static inline int snd_dice_transaction_read_sync(struct snd_dice *dice, unsigned int offset, void *buf, unsigned int len) { return snd_dice_transaction_read(dice, SND_DICE_ADDR_TYPE_SYNC, offset, buf, len); } int snd_dice_transaction_get_clock_source(struct snd_dice *dice, unsigned int *source); int snd_dice_transaction_get_rate(struct snd_dice *dice, unsigned int *rate); int snd_dice_transaction_set_enable(struct snd_dice *dice); void snd_dice_transaction_clear_enable(struct snd_dice *dice); int snd_dice_transaction_init(struct snd_dice *dice); int snd_dice_transaction_reinit(struct snd_dice *dice); void snd_dice_transaction_destroy(struct snd_dice *dice); #define SND_DICE_RATES_COUNT 7 extern const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT]; int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate); void snd_dice_stream_stop_duplex(struct snd_dice *dice); int snd_dice_stream_init_duplex(struct snd_dice *dice); void snd_dice_stream_destroy_duplex(struct snd_dice *dice); void snd_dice_stream_update_duplex(struct snd_dice *dice); int snd_dice_stream_lock_try(struct snd_dice *dice); void snd_dice_stream_lock_release(struct snd_dice *dice); int snd_dice_create_pcm(struct snd_dice *dice); int snd_dice_create_hwdep(struct snd_dice *dice); void snd_dice_create_proc(struct snd_dice *dice); int snd_dice_create_midi(struct snd_dice *dice); #endif 9dc2485053166e02c4aea01eb'>bcm-ns2.h2915logplain -rw-r--r--bcm-nsp.h2148logplain -rw-r--r--bcm21664.h1984logplain -rw-r--r--bcm281xx.h2456logplain -rw-r--r--bcm2835-aux.h635logplain -rw-r--r--bcm2835.h1962logplain -rw-r--r--berlin2.h1034logplain -rw-r--r--berlin2q.h695logplain -rw-r--r--clps711x-clock.h718logplain -rw-r--r--efm32-cmu.h1112logplain -rw-r--r--exynos-audss-clk.h597logplain -rw-r--r--exynos3250.h9083logplain -rw-r--r--exynos4.h8284logplain -rw-r--r--exynos4415.h9828logplain -rw-r--r--exynos5250.h4616logplain -rw-r--r--exynos5260-clk.h14876logplain -rw-r--r--exynos5410.h1689logplain -rw-r--r--exynos5420.h6857logplain -rw-r--r--exynos5433.h45372logplain -rw-r--r--exynos5440.h1141logplain -rw-r--r--exynos7-clk.h5281logplain -rw-r--r--gxbb-aoclkc.h2866logplain -rw-r--r--gxbb-clkc.h592logplain -rw-r--r--hi3516cv300-clock.h1668logplain -rw-r--r--hi3519-clock.h1328logplain -rw-r--r--hi3620-clock.h4496logplain -rw-r--r--hi6220-clock.h4508logplain -rw-r--r--hip04-clock.h1137logplain -rw-r--r--histb-clock.h2012logplain -rw-r--r--hix5hd2-clock.h2415logplain -rw-r--r--imx1-clock.h1055logplain -rw-r--r--imx21-clock.h2461logplain -rw-r--r--imx27-clock.h3494logplain -rw-r--r--imx5-clock.h7212logplain -rw-r--r--imx6qdl-clock.h9593logplain -rw-r--r--imx6sl-clock.h5849logplain -rw-r--r--imx6sx-clock.h9099logplain -rw-r--r--imx6ul-clock.h8203logplain -rw-r--r--imx7d-clock.h15974logplain -rw-r--r--jz4740-cgu.h1028logplain -rw-r--r--jz4780-cgu.h2470logplain -rw-r--r--lpc18xx-ccu.h2134logplain -rw-r--r--lpc18xx-cgu.h1142logplain -rw-r--r--lpc32xx-clock.h1633logplain -rw-r--r--lsi,axm5516-clks.h974logplain -rw-r--r--marvell,mmp2.h2022logplain -rw-r--r--marvell,pxa168.h1654logplain -rw-r--r--marvell,pxa1928.h1535logplain -rw-r--r--marvell,pxa910.h1598logplain -rw-r--r--maxim,max77620.h632logplain -rw-r--r--maxim,max77686.h648logplain -rw-r--r--maxim,max77802.h630logplain -rw-r--r--meson8b-clkc.h523logplain -rw-r--r--microchip,pic32-clock.h1150logplain -rw-r--r--mpc512x-clock.h2236logplain -rw-r--r--mt2701-clk.h13832logplain -rw-r--r--mt8135-clk.h5641logplain -rw-r--r--mt8173-clk.h9293logplain -rw-r--r--oxsemi,ox810se.h1002logplain -rw-r--r--oxsemi,ox820.h1203logplain -rw-r--r--pistachio-clk.h4863logplain -rw-r--r--pxa-clock.h1715logplain -rw-r--r--qcom,gcc-apq8084.h12872logplain -rw-r--r--qcom,gcc-ipq4019.h5423logplain -rw-r--r--qcom,gcc-ipq806x.h8574logplain -rw-r--r--qcom,gcc-mdm9615.h9497logplain -rw-r--r--qcom,gcc-msm8660.h7932logplain -rw-r--r--qcom,gcc-msm8916.h6190logplain -rw-r--r--qcom,gcc-msm8960.h9342logplain -rw-r--r--qcom,gcc-msm8974.h12340logplain -rw-r--r--qcom,gcc-msm8994.h4858logplain -rw-r--r--qcom,gcc-msm8996.h12575logplain -rw-r--r--qcom,lcc-ipq806x.h899logplain -rw-r--r--qcom,lcc-mdm9615.h1701logplain -rw-r--r--qcom,lcc-msm8960.h1616logplain -rw-r--r--qcom,mmcc-apq8084.h5722logplain -rw-r--r--qcom,mmcc-msm8960.h4109logplain -rw-r--r--qcom,mmcc-msm8974.h5223logplain -rw-r--r--qcom,mmcc-msm8996.h9403logplain -rw-r--r--qcom,rpmcc.h2101logplain -rw-r--r--r7s72100-clock.h1218logplain -rw-r--r--r8a73a4-clock.h1596logplain -rw-r--r--r8a7740-clock.h1992logplain -rw-r--r--r8a7743-cpg-mssr.h1269logplain -rw-r--r--r8a7745-cpg-mssr.h1298logplain -rw-r--r--r8a7778-clock.h1855logplain -rw-r--r--r8a7779-clock.h1647logplain -rw-r--r--r8a7790-clock.h4367logplain -rw-r--r--r8a7791-clock.h4388logplain -rw-r--r--r8a7792-clock.h2562logplain -rw-r--r--r8a7793-clock.h4561logplain -rw-r--r--r8a7794-clock.h3679logplain -rw-r--r--r8a7795-cpg-mssr.h1890logplain -rw-r--r--r8a7796-cpg-mssr.h2066logplain -rw-r--r--renesas-cpg-mssr.h542logplain -rw-r--r--rk1108-cru.h6605logplain -rw-r--r--rk3036-cru.h4584logplain -rw-r--r--rk3066a-cru.h1068logplain -rw-r--r--rk3188-cru-common.h6105logplain -rw-r--r--rk3188-cru.h1435logplain