/* * digi00x.h - a part of driver for Digidesign Digi 002/003 family * * Copyright (c) 2014-2015 Takashi Sakamoto * * Licensed under the terms of the GNU General Public License, version 2. */ #ifndef SOUND_DIGI00X_H_INCLUDED #define SOUND_DIGI00X_H_INCLUDED #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../lib.h" #include "../iso-resources.h" #include "../amdtp-stream.h" struct snd_dg00x { struct snd_card *card; struct fw_unit *unit; struct mutex mutex; spinlock_t lock; bool registered; struct delayed_work dwork; struct amdtp_stream tx_stream; struct fw_iso_resources tx_resources; struct amdtp_stream rx_stream; struct fw_iso_resources rx_resources; unsigned int substreams_counter; /* for uapi */ int dev_lock_count; bool dev_lock_changed; wait_queue_head_t hwdep_wait; /* For asynchronous messages. */ struct fw_address_handler async_handler; u32 msg; /* For asynchronous MIDI controls. */ struct snd_rawmidi_substream *in_control; struct snd_fw_async_midi_port out_control; }; #define DG00X_ADDR_BASE 0xffffe0000000ull #define DG00X_OFFSET_STREAMING_STATE 0x0000 #define DG00X_OFFSET_STREAMING_SET 0x0004 #define DG00X_OFFSET_MIDI_CTL_ADDR 0x0008 /* For LSB of the address 0x000c */ /* unknown 0x0010 */ #define DG00X_OFFSET_MESSAGE_ADDR 0x0014 /* For LSB of the address 0x0018 */ /* unknown 0x001c */ /* unknown 0x0020 */ /* not used 0x0024--0x00ff */ #define DG00X_OFFSET_ISOC_CHANNELS 0x0100 /* unknown 0x0104 */ /* unknown 0x0108 */ /* unknown 0x010c */ #define DG00X_OFFSET_LOCAL_RATE 0x0110 #define DG00X_OFFSET_EXTERNAL_RATE 0x0114 #define DG00X_OFFSET_CLOCK_SOURCE 0x0118 #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c /* unknown 0x0120 */ /* Mixer control on/off 0x0124 */ /* unknown 0x0128 */ #define DG00X_OFFSET_DETECT_EXTERNAL 0x012c /* unknown 0x0138 */ #define DG00X_OFFSET_MMC 0x0400 enum snd_dg00x_rate { SND_DG00X_RATE_44100 = 0, SND_DG00X_RATE_48000, SND_DG00X_RATE_88200, SND_DG00X_RATE_96000, SND_DG00X_RATE_COUNT, }; enum snd_dg00x_clock { SND_DG00X_CLOCK_INTERNAL = 0, SND_DG00X_CLOCK_SPDIF, SND_DG00X_CLOCK_ADAT, SND_DG00X_CLOCK_WORD, SND_DG00X_CLOCK_COUNT, }; enum snd_dg00x_optical_mode { SND_DG00X_OPT_IFACE_MODE_ADAT = 0, SND_DG00X_OPT_IFACE_MODE_SPDIF, SND_DG00X_OPT_IFACE_MODE_COUNT, }; #define DOT_MIDI_IN_PORTS 1 #define DOT_MIDI_OUT_PORTS 2 int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit, enum amdtp_stream_direction dir); int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate, unsigned int pcm_channels); void amdtp_dot_reset(struct amdtp_stream *s); int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s, struct snd_pcm_runtime *runtime); void amdtp_dot_set_pcm_format(struct amdtp_stream *s, snd_pcm_format_t format); void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port, struct snd_rawmidi_substream *midi); int snd_dg00x_transaction_register(struct snd_dg00x *dg00x); int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x); void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x); extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT]; extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT]; int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x, unsigned int *rate); int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x, unsigned int *rate); int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate); int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x, enum snd_dg00x_clock *clock); int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x, bool *detect); int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x); int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x, unsigned int rate); void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x); void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x); void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x); void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x); int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x); void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x); void snd_dg00x_proc_init(struct snd_dg00x *dg00x); int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x); int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x); int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x); #endif form>
authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /sound/oss/kahlua.c
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'sound/oss/kahlua.c')