#ifndef AU88X0_EQ_H #define AU88X0_EQ_H /*************************************************************************** * au88x0_eq.h * * Definitions and constant data for the Aureal Hardware EQ. * * Sun Jun 8 18:23:38 2003 * Author: Manuel Jander (mjander@users.sourceforge.net) ****************************************************************************/ typedef struct { u16 LeftCoefs[50]; //0x4 u16 RightCoefs[50]; // 0x68 u16 LeftGains[10]; //0xd0 u16 RightGains[10]; //0xe4 } auxxEqCoeffSet_t; typedef struct { s32 this04; /* How many filters for each side (default = 10) */ s32 this08; /* inited to cero. Stereo flag? */ } eqhw_t; typedef struct { eqhw_t this04; /* CHwEq */ u16 this08; /* Bad codec flag ? SetBypassGain: bypass gain */ u16 this0a; u16 this0c; /* SetBypassGain: bypass gain when this28 is not set. */ u16 this0e; s32 this10; /* How many gains are used for each side (right or left). */ u16 this14_array[10]; /* SetLeftGainsTarget: Left (and right?) EQ gains */ s32 this28; /* flag related to EQ enabled or not. Gang flag ? */ s32 this54; /* SetBypass */ s32 this58; s32 this5c; /*0x60 */ auxxEqCoeffSet_t coefset; /* 50 u16 word each channel. */ u16 this130[20]; /* Left and Right gains */ } eqlzr_t; #endif cket-loop-back'>packet-loop-back net-next plumbingsTobias Klauser
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authorBorislav Petkov <bp@suse.de>2017-01-20 21:29:40 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-23 09:39:55 +0100
commitc26665ab5c49ad3e142e0f054ca3204f259ba09c (patch)
tree3bab11918e18e9d25ef7544dba05cdf39d1abec5 /net/netlink/genetlink.c
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in the initrd since the first AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'net/netlink/genetlink.c')