#ifndef __SOUND_PHASE_H #define __SOUND_PHASE_H /* * ALSA driver for ICEnsemble ICE1712 (Envy24) * * Lowlevel functions for Terratec PHASE 22 * * Copyright (c) 2005 Misha Zhilin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\ "{Terratec,Phase 28},"\ "{Terrasoniq,TS22}," #define VT1724_SUBDEVICE_PHASE22 0x3b155011 #define VT1724_SUBDEVICE_PHASE28 0x3b154911 #define VT1724_SUBDEVICE_TS22 0x3b157b11 /* entry point */ extern struct snd_ice1712_card_info snd_vt1724_phase_cards[]; /* PHASE28 GPIO bits */ #define PHASE28_SPI_MISO (1 << 21) #define PHASE28_WM_RESET (1 << 20) #define PHASE28_SPI_CLK (1 << 19) #define PHASE28_SPI_MOSI (1 << 18) #define PHASE28_WM_RW (1 << 17) #define PHASE28_AC97_RESET (1 << 16) #define PHASE28_DIGITAL_SEL1 (1 << 15) #define PHASE28_HP_SEL (1 << 14) #define PHASE28_WM_CS (1 << 12) #define PHASE28_AC97_COMMIT (1 << 11) #define PHASE28_AC97_ADDR (1 << 10) #define PHASE28_AC97_DATA_LOW (1 << 9) #define PHASE28_AC97_DATA_HIGH (1 << 8) #define PHASE28_AC97_DATA_MASK 0xFF #endif /* __SOUND_PHASE */ 946b85274e35c9757'>treecommitdiff
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authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /include/net/irda/ircomm_core.h
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'include/net/irda/ircomm_core.h')