#ifndef CS2000_H_INCLUDED #define CS2000_H_INCLUDED #define CS2000_DEV_ID 0x01 #define CS2000_DEV_CTRL 0x02 #define CS2000_DEV_CFG_1 0x03 #define CS2000_DEV_CFG_2 0x04 #define CS2000_GLOBAL_CFG 0x05 #define CS2000_RATIO_0 0x06 /* 32 bits, big endian */ #define CS2000_RATIO_1 0x0a #define CS2000_RATIO_2 0x0e #define CS2000_RATIO_3 0x12 #define CS2000_FUN_CFG_1 0x16 #define CS2000_FUN_CFG_2 0x17 #define CS2000_FUN_CFG_3 0x1e /* DEV_ID */ #define CS2000_DEVICE_MASK 0xf8 #define CS2000_REVISION_MASK 0x07 /* DEV_CTRL */ #define CS2000_UNLOCK 0x80 #define CS2000_AUX_OUT_DIS 0x02 #define CS2000_CLK_OUT_DIS 0x01 /* DEV_CFG_1 */ #define CS2000_R_MOD_SEL_MASK 0xe0 #define CS2000_R_MOD_SEL_1 0x00 #define CS2000_R_MOD_SEL_2 0x20 #define CS2000_R_MOD_SEL_4 0x40 #define CS2000_R_MOD_SEL_8 0x60 #define CS2000_R_MOD_SEL_1_2 0x80 #define CS2000_R_MOD_SEL_1_4 0xa0 #define CS2000_R_MOD_SEL_1_8 0xc0 #define CS2000_R_MOD_SEL_1_16 0xe0 #define CS2000_R_SEL_MASK 0x18 #define CS2000_R_SEL_SHIFT 3 #define CS2000_AUX_OUT_SRC_MASK 0x06 #define CS2000_AUX_OUT_SRC_REF_CLK 0x00 #define CS2000_AUX_OUT_SRC_CLK_IN 0x02 #define CS2000_AUX_OUT_SRC_CLK_OUT 0x04 #define CS2000_AUX_OUT_SRC_PLL_LOCK 0x06 #define CS2000_EN_DEV_CFG_1 0x01 /* DEV_CFG_2 */ #define CS2000_LOCK_CLK_MASK 0x06 #define CS2000_LOCK_CLK_SHIFT 1 #define CS2000_FRAC_N_SRC_MASK 0x01 #define CS2000_FRAC_N_SRC_STATIC 0x00 #define CS2000_FRAC_N_SRC_DYNAMIC 0x01 /* GLOBAL_CFG */ #define CS2000_FREEZE 0x08 #define CS2000_EN_DEV_CFG_2 0x01 /* FUN_CFG_1 */ #define CS2000_CLK_SKIP_EN 0x80 #define CS2000_AUX_LOCK_CFG_MASK 0x40 #define CS2000_AUX_LOCK_CFG_PP_HIGH 0x00 #define CS2000_AUX_LOCK_CFG_OD_LOW 0x40 #define CS2000_REF_CLK_DIV_MASK 0x18 #define CS2000_REF_CLK_DIV_4 0x00 #define CS2000_REF_CLK_DIV_2 0x08 #define CS2000_REF_CLK_DIV_1 0x10 /* FUN_CFG_2 */ #define CS2000_CLK_OUT_UNL 0x10 #define CS2000_L_F_RATIO_CFG_MASK 0x08 #define CS2000_L_F_RATIO_CFG_20_12 0x00 #define CS2000_L_F_RATIO_CFG_12_20 0x08 /* FUN_CFG_3 */ #define CS2000_CLK_IN_BW_MASK 0x70 #define CS2000_CLK_IN_BW_1 0x00 #define CS2000_CLK_IN_BW_2 0x10 #define CS2000_CLK_IN_BW_4 0x20 #define CS2000_CLK_IN_BW_8 0x30 #define CS2000_CLK_IN_BW_16 0x40 #define CS2000_CLK_IN_BW_32 0x50 #define CS2000_CLK_IN_BW_64 0x60 #define CS2000_CLK_IN_BW_128 0x70 #endif ext.git/log/net/ethernet/eth.c'>
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authorIago Abal <mail@iagoabal.eu>2017-01-11 14:00:21 +0100
committerVinod Koul <vinod.koul@intel.com>2017-01-25 15:35:11 +0530
commit91539eb1fda2d530d3b268eef542c5414e54bf1a (patch)
tree960f5ca6342ad20837aff18aad6e8ecd7da32fd6 /net/ethernet/eth.c
parent6610d0edf6dc7ee97e46ab3a538a565c79d26199 (diff)
dmaengine: pl330: fix double lock
The static bug finder EBA (http://www.iagoabal.eu/eba/) reported the following double-lock bug: Double lock: 1. spin_lock_irqsave(pch->lock, flags) at pl330_free_chan_resources:2236; 2. call to function `pl330_release_channel' immediately after; 3. call to function `dma_pl330_rqcb' in line 1753; 4. spin_lock_irqsave(pch->lock, flags) at dma_pl330_rqcb:1505. I have fixed it as suggested by Marek Szyprowski. First, I have replaced `pch->lock' with `pl330->lock' in functions `pl330_alloc_chan_resources' and `pl330_free_chan_resources'. This avoids the double-lock by acquiring a different lock than `dma_pl330_rqcb'. NOTE that, as a result, `pl330_free_chan_resources' executes `list_splice_tail_init' on `pch->work_list' under lock `pl330->lock', whereas in the rest of the code `pch->work_list' is protected by `pch->lock'. I don't know if this may cause race conditions. Similarly `pch->cyclic' is written by `pl330_alloc_chan_resources' under `pl330->lock' but read by `pl330_tx_submit' under `pch->lock'. Second, I have removed locking from `pl330_request_channel' and `pl330_release_channel' functions. Function `pl330_request_channel' is only called from `pl330_alloc_chan_resources', so the lock is already held. Function `pl330_release_channel' is called from `pl330_free_chan_resources', which already holds the lock, and from `pl330_del'. Function `pl330_del' is called in an error path of `pl330_probe' and at the end of `pl330_remove', but I assume that there cannot be concurrent accesses to the protected data at those points. Signed-off-by: Iago Abal <mail@iagoabal.eu> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'net/ethernet/eth.c')