/* register 01h */ #define CS4362A_PDN 0x01 #define CS4362A_DAC1_DIS 0x02 #define CS4362A_DAC2_DIS 0x04 #define CS4362A_DAC3_DIS 0x08 #define CS4362A_MCLKDIV 0x20 #define CS4362A_FREEZE 0x40 #define CS4362A_CPEN 0x80 /* register 02h */ #define CS4362A_DIF_MASK 0x70 #define CS4362A_DIF_LJUST 0x00 #define CS4362A_DIF_I2S 0x10 #define CS4362A_DIF_RJUST_16 0x20 #define CS4362A_DIF_RJUST_24 0x30 #define CS4362A_DIF_RJUST_20 0x40 #define CS4362A_DIF_RJUST_18 0x50 /* register 03h */ #define CS4362A_MUTEC_MASK 0x03 #define CS4362A_MUTEC_6 0x00 #define CS4362A_MUTEC_1 0x01 #define CS4362A_MUTEC_3 0x03 #define CS4362A_AMUTE 0x04 #define CS4362A_MUTEC_POL 0x08 #define CS4362A_RMP_UP 0x10 #define CS4362A_SNGLVOL 0x20 #define CS4362A_ZERO_CROSS 0x40 #define CS4362A_SOFT_RAMP 0x80 /* register 04h */ #define CS4362A_RMP_DN 0x01 #define CS4362A_DEM_MASK 0x06 #define CS4362A_DEM_NONE 0x00 #define CS4362A_DEM_44100 0x02 #define CS4362A_DEM_48000 0x04 #define CS4362A_DEM_32000 0x06 #define CS4362A_FILT_SEL 0x10 /* register 05h */ #define CS4362A_INV_A1 0x01 #define CS4362A_INV_B1 0x02 #define CS4362A_INV_A2 0x04 #define CS4362A_INV_B2 0x08 #define CS4362A_INV_A3 0x10 #define CS4362A_INV_B3 0x20 /* register 06h */ #define CS4362A_FM_MASK 0x03 #define CS4362A_FM_SINGLE 0x00 #define CS4362A_FM_DOUBLE 0x01 #define CS4362A_FM_QUAD 0x02 #define CS4362A_FM_DSD 0x03 #define CS4362A_ATAPI_MASK 0x7c #define CS4362A_ATAPI_B_MUTE 0x00 #define CS4362A_ATAPI_B_R 0x04 #define CS4362A_ATAPI_B_L 0x08 #define CS4362A_ATAPI_B_LR 0x0c #define CS4362A_ATAPI_A_MUTE 0x00 #define CS4362A_ATAPI_A_R 0x10 #define CS4362A_ATAPI_A_L 0x20 #define CS4362A_ATAPI_A_LR 0x30 #define CS4362A_ATAPI_MIX_LR_VOL 0x40 #define CS4362A_A_EQ_B 0x80 /* register 07h */ #define CS4362A_VOL_MASK 0x7f #define CS4362A_MUTE 0x80 /* register 08h: like 07h */ /* registers 09h..0Bh: like 06h..08h */ /* registers 0Ch..0Eh: like 06h..08h */ /* register 12h */ #define CS4362A_REV_MASK 0x07 #define CS4362A_PART_MASK 0xf8 #define CS4362A_PART_CS4362A 0x50 89d1144'>commitdiff
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /sound/soc/codecs/da7218.h
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'sound/soc/codecs/da7218.h')