#ifndef PCM1796_H_INCLUDED #define PCM1796_H_INCLUDED /* register 16 */ #define PCM1796_ATL_MASK 0xff /* register 17 */ #define PCM1796_ATR_MASK 0xff /* register 18 */ #define PCM1796_MUTE 0x01 #define PCM1796_DME 0x02 #define PCM1796_DMF_MASK 0x0c #define PCM1796_DMF_DISABLED 0x00 #define PCM1796_DMF_48 0x04 #define PCM1796_DMF_441 0x08 #define PCM1796_DMF_32 0x0c #define PCM1796_FMT_MASK 0x70 #define PCM1796_FMT_16_RJUST 0x00 #define PCM1796_FMT_20_RJUST 0x10 #define PCM1796_FMT_24_RJUST 0x20 #define PCM1796_FMT_24_LJUST 0x30 #define PCM1796_FMT_16_I2S 0x40 #define PCM1796_FMT_24_I2S 0x50 #define PCM1796_ATLD 0x80 /* register 19 */ #define PCM1796_INZD 0x01 #define PCM1796_FLT_MASK 0x02 #define PCM1796_FLT_SHARP 0x00 #define PCM1796_FLT_SLOW 0x02 #define PCM1796_DFMS 0x04 #define PCM1796_OPE 0x10 #define PCM1796_ATS_MASK 0x60 #define PCM1796_ATS_1 0x00 #define PCM1796_ATS_2 0x20 #define PCM1796_ATS_4 0x40 #define PCM1796_ATS_8 0x60 #define PCM1796_REV 0x80 /* register 20 */ #define PCM1796_OS_MASK 0x03 #define PCM1796_OS_64 0x00 #define PCM1796_OS_32 0x01 #define PCM1796_OS_128 0x02 #define PCM1796_CHSL_MASK 0x04 #define PCM1796_CHSL_LEFT 0x00 #define PCM1796_CHSL_RIGHT 0x04 #define PCM1796_MONO 0x08 #define PCM1796_DFTH 0x10 #define PCM1796_DSD 0x20 #define PCM1796_SRST 0x40 /* register 21 */ #define PCM1796_PCMZ 0x01 #define PCM1796_DZ_MASK 0x06 /* register 22 */ #define PCM1796_ZFGL 0x01 #define PCM1796_ZFGR 0x02 /* register 23 */ #define PCM1796_ID_MASK 0x1f #endif
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authorBorislav Petkov <bp@suse.de>2017-01-20 21:29:40 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-23 09:39:55 +0100
commitc26665ab5c49ad3e142e0f054ca3204f259ba09c (patch)
tree3bab11918e18e9d25ef7544dba05cdf39d1abec5 /sound/usb/endpoint.c
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in the initrd since the first AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'sound/usb/endpoint.c')