/* * atmel_ssc_dai.h - ALSA SSC interface for the Atmel SoC * * Copyright (C) 2005 SAN People * Copyright (C) 2008 Atmel * * Author: Sedji Gaouaou * ATMEL CORP. * * Based on at91-ssc.c by * Frank Mandarino * Based on pxa2xx Platform drivers by * Liam Girdwood * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ATMEL_SSC_DAI_H #define _ATMEL_SSC_DAI_H #include #include #include "atmel-pcm.h" /* SSC system clock ids */ #define ATMEL_SYSCLK_MCK 0 /* SSC uses AT91 MCK as system clock */ /* SSC divider ids */ #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */ #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */ #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */ /* * SSC direction masks */ #define SSC_DIR_MASK_UNUSED 0 #define SSC_DIR_MASK_PLAYBACK 1 #define SSC_DIR_MASK_CAPTURE 2 /* * SSC register values that Atmel left out of . These * are expected to be used with SSC_BF */ /* START bit field values */ #define SSC_START_CONTINUOUS 0 #define SSC_START_TX_RX 1 #define SSC_START_LOW_RF 2 #define SSC_START_HIGH_RF 3 #define SSC_START_FALLING_RF 4 #define SSC_START_RISING_RF 5 #define SSC_START_LEVEL_RF 6 #define SSC_START_EDGE_RF 7 #define SSS_START_COMPARE_0 8 /* CKI bit field values */ #define SSC_CKI_FALLING 0 #define SSC_CKI_RISING 1 /* CKO bit field values */ #define SSC_CKO_NONE 0 #define SSC_CKO_CONTINUOUS 1 #define SSC_CKO_TRANSFER 2 /* CKS bit field values */ #define SSC_CKS_DIV 0 #define SSC_CKS_CLOCK 1 #define SSC_CKS_PIN 2 /* FSEDGE bit field values */ #define SSC_FSEDGE_POSITIVE 0 #define SSC_FSEDGE_NEGATIVE 1 /* FSOS bit field values */ #define SSC_FSOS_NONE 0 #define SSC_FSOS_NEGATIVE 1 #define SSC_FSOS_POSITIVE 2 #define SSC_FSOS_LOW 3 #define SSC_FSOS_HIGH 4 #define SSC_FSOS_TOGGLE 5 #define START_DELAY 1 struct atmel_ssc_state { u32 ssc_cmr; u32 ssc_rcmr; u32 ssc_rfmr; u32 ssc_tcmr; u32 ssc_tfmr; u32 ssc_sr; u32 ssc_imr; }; struct atmel_ssc_info { char *name; struct ssc_device *ssc; spinlock_t lock; /* lock for dir_mask */ unsigned short dir_mask; /* 0=unused, 1=playback, 2=capture */ unsigned short initialized; /* true if SSC has been initialized */ unsigned short daifmt; unsigned short cmr_div; unsigned short tcmr_period; unsigned short rcmr_period; unsigned int forced_divider; struct atmel_pcm_dma_params *dma_params[2]; struct atmel_ssc_state ssc_state; unsigned long mck_rate; }; int atmel_ssc_set_audio(int ssc_id); void atmel_ssc_put_audio(int ssc_id); #endif /* _AT91_SSC_DAI_H */ f1d93e968ee3'/>
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /net/vmw_vsock/vmci_transport.c
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'net/vmw_vsock/vmci_transport.c')