/* * 88pm860x-codec.h -- 88PM860x ALSA SoC Audio Driver * * Copyright 2010 Marvell International Ltd. * Haojian Zhuang * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __88PM860X_H #define __88PM860X_H #define PM860X_PCM_IFACE_1 0xb0 #define PM860X_PCM_IFACE_2 0xb1 #define PM860X_PCM_IFACE_3 0xb2 #define PM860X_PCM_RATE 0xb3 #define PM860X_EC_PATH 0xb4 #define PM860X_SIDETONE_L_GAIN 0xb5 #define PM860X_SIDETONE_R_GAIN 0xb6 #define PM860X_SIDETONE_SHIFT 0xb7 #define PM860X_ADC_OFFSET_1 0xb8 #define PM860X_ADC_OFFSET_2 0xb9 #define PM860X_DMIC_DELAY 0xba #define PM860X_I2S_IFACE_1 0xbb #define PM860X_I2S_IFACE_2 0xbc #define PM860X_I2S_IFACE_3 0xbd #define PM860X_I2S_IFACE_4 0xbe #define PM860X_EQUALIZER_N0_1 0xbf #define PM860X_EQUALIZER_N0_2 0xc0 #define PM860X_EQUALIZER_N1_1 0xc1 #define PM860X_EQUALIZER_N1_2 0xc2 #define PM860X_EQUALIZER_D1_1 0xc3 #define PM860X_EQUALIZER_D1_2 0xc4 #define PM860X_LOFI_GAIN_LEFT 0xc5 #define PM860X_LOFI_GAIN_RIGHT 0xc6 #define PM860X_HIFIL_GAIN_LEFT 0xc7 #define PM860X_HIFIL_GAIN_RIGHT 0xc8 #define PM860X_HIFIR_GAIN_LEFT 0xc9 #define PM860X_HIFIR_GAIN_RIGHT 0xca #define PM860X_DAC_OFFSET 0xcb #define PM860X_OFFSET_LEFT_1 0xcc #define PM860X_OFFSET_LEFT_2 0xcd #define PM860X_OFFSET_RIGHT_1 0xce #define PM860X_OFFSET_RIGHT_2 0xcf #define PM860X_ADC_ANA_1 0xd0 #define PM860X_ADC_ANA_2 0xd1 #define PM860X_ADC_ANA_3 0xd2 #define PM860X_ADC_ANA_4 0xd3 #define PM860X_ANA_TO_ANA 0xd4 #define PM860X_HS1_CTRL 0xd5 #define PM860X_HS2_CTRL 0xd6 #define PM860X_LO1_CTRL 0xd7 #define PM860X_LO2_CTRL 0xd8 #define PM860X_EAR_CTRL_1 0xd9 #define PM860X_EAR_CTRL_2 0xda #define PM860X_AUDIO_SUPPLIES_1 0xdb #define PM860X_AUDIO_SUPPLIES_2 0xdc #define PM860X_ADC_EN_1 0xdd #define PM860X_ADC_EN_2 0xde #define PM860X_DAC_EN_1 0xdf #define PM860X_DAC_EN_2 0xe1 #define PM860X_AUDIO_CAL_1 0xe2 #define PM860X_AUDIO_CAL_2 0xe3 #define PM860X_AUDIO_CAL_3 0xe4 #define PM860X_AUDIO_CAL_4 0xe5 #define PM860X_AUDIO_CAL_5 0xe6 #define PM860X_ANA_INPUT_SEL_1 0xe7 #define PM860X_ANA_INPUT_SEL_2 0xe8 #define PM860X_PCM_IFACE_4 0xe9 #define PM860X_I2S_IFACE_5 0xea #define PM860X_SHORTS 0x3b #define PM860X_PLL_ADJ_1 0x3c #define PM860X_PLL_ADJ_2 0x3d /* bits definition */ #define PM860X_CLK_DIR_IN 0 #define PM860X_CLK_DIR_OUT 1 #define PM860X_DET_HEADSET (1 << 0) #define PM860X_DET_MIC (1 << 1) #define PM860X_DET_HOOK (1 << 2) #define PM860X_SHORT_HEADSET (1 << 3) #define PM860X_SHORT_LINEOUT (1 << 4) #define PM860X_DET_MASK 0x1F extern int pm860x_hs_jack_detect(struct snd_soc_codec *, struct snd_soc_jack *, int, int, int, int); extern int pm860x_mic_jack_detect(struct snd_soc_codec *, struct snd_soc_jack *, int); #endif /* __88PM860X_H */ >space:mode:
authorLars-Peter Clausen <lars@metafoo.de>2016-06-15 15:07:27 +0200
committerMark Brown <broonie@kernel.org>2016-06-15 14:42:40 +0100
commit5d76de61dd8cb89b7189ef7456fba921c547c398 (patch)
tree3d85cae578faa5a1137227bad4ad2eb355c30728
parent0eadaa9ce2aacdcc3cf050d98c25aacabadc557f (diff)
ASoC: adau17x1: Add support for specifying the MCLK using the CCF
The devices from the ADAU17X1 family all have a MCLK clock input which supplies the master clock for the device. The master clock is used as the input clock for the PLL. Currently the MCLK rate as well as the desired PLL output frequency need to be supplied by calling snd_soc_dai_set_pll() form a machine driver. Add support for specifying the MCLK using the common clock framework. In addition to that also automatically configure the PLL to a suitable rate if the master clock was provided using the CCW. This allows to use the CODEC driver without any special configuration requirements from the machine driver. While the PLL output frequency can be configured over a (more or less) continuous range the narrowness of the range and the other constraints of the clocking tree usually only result in two output frequencies that will actually be chosen. One for 44.1kHz based rates and one for 48kHz based rates, these are the rates that the automatic PLL configuration will use. For the rare case where a non-standard setup is required a machine driver can disable the auto-configuration and configure a custom frequency using the existing mechanisms. If the common clock framework is not enabled clk_get() will return NULL and the driver will function as before and the clock rate needs to be configured manually. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
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