/* * rl6347a.c - RL6347A class device shared support * * Copyright 2015 Realtek Semiconductor Corp. * * Author: Oder Chiou * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include "rl6347a.h" int rl6347a_hw_write(void *context, unsigned int reg, unsigned int value) { struct i2c_client *client = context; struct rl6347a_priv *rl6347a = i2c_get_clientdata(client); u8 data[4]; int ret, i; /* handle index registers */ if (reg <= 0xff) { rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg); for (i = 0; i < rl6347a->index_cache_size; i++) { if (reg == rl6347a->index_cache[i].reg) { rl6347a->index_cache[i].def = value; break; } } reg = RL6347A_PROC_COEF; } data[0] = (reg >> 24) & 0xff; data[1] = (reg >> 16) & 0xff; /* * 4 bit VID: reg should be 0 * 12 bit VID: value should be 0 * So we use an OR operator to handle it rather than use if condition. */ data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); data[3] = value & 0xff; ret = i2c_master_send(client, data, 4); if (ret == 4) return 0; else dev_err(&client->dev, "I2C error %d\n", ret); if (ret < 0) return ret; else return -EIO; } EXPORT_SYMBOL_GPL(rl6347a_hw_write); int rl6347a_hw_read(void *context, unsigned int reg, unsigned int *value) { struct i2c_client *client = context; struct i2c_msg xfer[2]; int ret; __be32 be_reg; unsigned int index, vid, buf = 0x0; /* handle index registers */ if (reg <= 0xff) { rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg); reg = RL6347A_PROC_COEF; } reg = reg | 0x80000; vid = (reg >> 8) & 0xfff; if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { index = (reg >> 8) & 0xf; reg = (reg & ~0xf0f) | index; } be_reg = cpu_to_be32(reg); /* Write register */ xfer[0].addr = client->addr; xfer[0].flags = 0; xfer[0].len = 4; xfer[0].buf = (u8 *)&be_reg; /* Read data */ xfer[1].addr = client->addr; xfer[1].flags = I2C_M_RD; xfer[1].len = 4; xfer[1].buf = (u8 *)&buf; ret = i2c_transfer(client->adapter, xfer, 2); if (ret < 0) return ret; else if (ret != 2) return -EIO; *value = be32_to_cpu(buf); return 0; } EXPORT_SYMBOL_GPL(rl6347a_hw_read); MODULE_DESCRIPTION("RL6347A class device shared support"); MODULE_AUTHOR("Oder Chiou "); MODULE_LICENSE("GPL v2"); ac0764bd'/>
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authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /sound/soc/mediatek/common/mtk-afe-fe-dai.h
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'sound/soc/mediatek/common/mtk-afe-fe-dai.h')