/* * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver * * Copyright 2013 Realtek Semiconductor Corp. * Author: Oder Chiou * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "rt5677-spi.h" #define RT5677_SPI_BURST_LEN 240 #define RT5677_SPI_HEADER 5 #define RT5677_SPI_FREQ 6000000 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. * DataPhase word size of 16-bit commands is 2 bytes. * DataPhase word size of 32-bit commands is 4 bytes. * DataPhase word size of burst commands is 8 bytes. * The DSP CPU is little-endian. */ #define RT5677_SPI_WRITE_BURST 0x5 #define RT5677_SPI_READ_BURST 0x4 #define RT5677_SPI_WRITE_32 0x3 #define RT5677_SPI_READ_32 0x2 #define RT5677_SPI_WRITE_16 0x1 #define RT5677_SPI_READ_16 0x0 static struct spi_device *g_spi; static DEFINE_MUTEX(spi_mutex); /* Select a suitable transfer command for the next transfer to ensure * the transfer address is always naturally aligned while minimizing * the total number of transfers required. * * 3 transfer commands are available: * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes * * For example, reading 260 bytes at 0x60030002 uses the following commands: * 0x60030002 RT5677_SPI_READ_16 2 bytes * 0x60030004 RT5677_SPI_READ_32 4 bytes * 0x60030008 RT5677_SPI_READ_BURST 240 bytes * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes * 0x60030100 RT5677_SPI_READ_32 4 bytes * 0x60030104 RT5677_SPI_READ_16 2 bytes * * Input: * @read: true for read commands; false for write commands * @align: alignment of the next transfer address * @remain: number of bytes remaining to transfer * * Output: * @len: number of bytes to transfer with the selected command * Returns the selected command */ static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) { u8 cmd; if (align == 2 || align == 6 || remain == 2) { cmd = RT5677_SPI_READ_16; *len = 2; } else if (align == 4 || remain <= 6) { cmd = RT5677_SPI_READ_32; *len = 4; } else { cmd = RT5677_SPI_READ_BURST; *len = min_t(u32, remain & ~7, RT5677_SPI_BURST_LEN); } return read ? cmd : cmd + 1; } /* Copy dstlen bytes from src to dst, while reversing byte order for each word. * If srclen < dstlen, zeros are padded. */ static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) { u32 w, i, si; u32 word_size = min_t(u32, dstlen, 8); for (w = 0; w < dstlen; w += word_size) { for (i = 0; i < word_size; i++) { si = w + word_size - i - 1; dst[w + i] = si < srclen ? src[si] : 0; } } } /* Read DSP address space using SPI. addr and len have to be 2-byte aligned. */ int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) { u32 offset; int status = 0; struct spi_transfer t[2]; struct spi_message m; /* +4 bytes is for the DummyPhase following the AddressPhase */ u8 header[RT5677_SPI_HEADER + 4]; u8 body[RT5677_SPI_BURST_LEN]; u8 spi_cmd; u8 *cb = rxbuf; if (!g_spi) return -ENODEV; if ((addr & 1) || (len & 1)) { dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); return -EACCES; } memset(t, 0, sizeof(t)); t[0].tx_buf = header; t[0].len = sizeof(header); t[0].speed_hz = RT5677_SPI_FREQ; t[1].rx_buf = body; t[1].speed_hz = RT5677_SPI_FREQ; spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); for (offset = 0; offset < len; offset += t[1].len) { spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, len - offset, &t[1].len); /* Construct SPI message header */ header[0] = spi_cmd; header[1] = ((addr + offset) & 0xff000000) >> 24; header[2] = ((addr + offset) & 0x00ff0000) >> 16; header[3] = ((addr + offset) & 0x0000ff00) >> 8; header[4] = ((addr + offset) & 0x000000ff) >> 0; mutex_lock(&spi_mutex); status |= spi_sync(g_spi, &m); mutex_unlock(&spi_mutex); /* Copy data back to caller buffer */ rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len); } return status; } EXPORT_SYMBOL_GPL(rt5677_spi_read); /* Write DSP address space using SPI. addr has to be 2-byte aligned. * If len is not 2-byte aligned, an extra byte of zero is written at the end * as padding. */ int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) { u32 offset, len_with_pad = len; int status = 0; struct spi_transfer t; struct spi_message m; /* +1 byte is for the DummyPhase following the DataPhase */ u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; u8 *body = buf + RT5677_SPI_HEADER; u8 spi_cmd; const u8 *cb = txbuf; if (!g_spi) return -ENODEV; if (addr & 1) { dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); return -EACCES; } if (len & 1) len_with_pad = len + 1; memset(&t, 0, sizeof(t)); t.tx_buf = buf; t.speed_hz = RT5677_SPI_FREQ; spi_message_init_with_transfers(&m, &t, 1); for (offset = 0; offset < len_with_pad;) { spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, len_with_pad - offset, &t.len); /* Construct SPI message header */ buf[0] = spi_cmd; buf[1] = ((addr + offset) & 0xff000000) >> 24; buf[2] = ((addr + offset) & 0x00ff0000) >> 16; buf[3] = ((addr + offset) & 0x0000ff00) >> 8; buf[4] = ((addr + offset) & 0x000000ff) >> 0; /* Fetch data from caller buffer */ rt5677_spi_reverse(body, t.len, cb + offset, len - offset); offset += t.len; t.len += RT5677_SPI_HEADER + 1; mutex_lock(&spi_mutex); status |= spi_sync(g_spi, &m); mutex_unlock(&spi_mutex); } return status; } EXPORT_SYMBOL_GPL(rt5677_spi_write); int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) { return rt5677_spi_write(addr, fw->data, fw->size); } EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); static int rt5677_spi_probe(struct spi_device *spi) { g_spi = spi; return 0; } static struct spi_driver rt5677_spi_driver = { .driver = { .name = "rt5677", }, .probe = rt5677_spi_probe, }; module_spi_driver(rt5677_spi_driver); MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); MODULE_AUTHOR("Oder Chiou "); MODULE_LICENSE("GPL v2"); dings/clock/bcm-nsp.h?id=8ca967ab67671f07ac7daef4f854559bc66799a3'>bcm-nsp.h2148logplain -rw-r--r--bcm21664.h1984logplain -rw-r--r--bcm281xx.h2456logplain -rw-r--r--bcm2835-aux.h635logplain -rw-r--r--bcm2835.h1962logplain -rw-r--r--berlin2.h1034logplain -rw-r--r--berlin2q.h695logplain -rw-r--r--clps711x-clock.h718logplain -rw-r--r--efm32-cmu.h1112logplain -rw-r--r--exynos-audss-clk.h597logplain -rw-r--r--exynos3250.h9083logplain -rw-r--r--exynos4.h8284logplain -rw-r--r--exynos4415.h9828logplain -rw-r--r--exynos5250.h4616logplain -rw-r--r--exynos5260-clk.h14876logplain -rw-r--r--exynos5410.h1689logplain -rw-r--r--exynos5420.h6857logplain -rw-r--r--exynos5433.h45372logplain -rw-r--r--exynos5440.h1141logplain -rw-r--r--exynos7-clk.h5281logplain -rw-r--r--gxbb-aoclkc.h2866logplain -rw-r--r--gxbb-clkc.h592logplain -rw-r--r--hi3516cv300-clock.h1668logplain -rw-r--r--hi3519-clock.h1328logplain -rw-r--r--hi3620-clock.h4496logplain -rw-r--r--hi6220-clock.h4508logplain -rw-r--r--hip04-clock.h1137logplain -rw-r--r--histb-clock.h2012logplain -rw-r--r--hix5hd2-clock.h2415logplain -rw-r--r--imx1-clock.h1055logplain -rw-r--r--imx21-clock.h2461logplain -rw-r--r--imx27-clock.h3494logplain -rw-r--r--imx5-clock.h7212logplain -rw-r--r--imx6qdl-clock.h9593logplain -rw-r--r--imx6sl-clock.h5849logplain -rw-r--r--imx6sx-clock.h9099logplain -rw-r--r--imx6ul-clock.h8203logplain -rw-r--r--imx7d-clock.h15974logplain -rw-r--r--jz4740-cgu.h1028logplain -rw-r--r--jz4780-cgu.h2470logplain -rw-r--r--lpc18xx-ccu.h2134logplain -rw-r--r--lpc18xx-cgu.h1142logplain -rw-r--r--lpc32xx-clock.h1633logplain -rw-r--r--lsi,axm5516-clks.h974logplain -rw-r--r--marvell,mmp2.h2022logplain -rw-r--r--marvell,pxa168.h1654logplain -rw-r--r--marvell,pxa1928.h1535logplain -rw-r--r--marvell,pxa910.h1598logplain -rw-r--r--maxim,max77620.h632logplain -rw-r--r--maxim,max77686.h648logplain -rw-r--r--maxim,max77802.h630logplain -rw-r--r--meson8b-clkc.h523logplain -rw-r--r--microchip,pic32-clock.h1150logplain -rw-r--r--mpc512x-clock.h2236logplain -rw-r--r--mt2701-clk.h13832logplain -rw-r--r--mt8135-clk.h5641logplain -rw-r--r--mt8173-clk.h9293logplain -rw-r--r--oxsemi,ox810se.h1002logplain -rw-r--r--oxsemi,ox820.h1203logplain -rw-r--r--pistachio-clk.h4863logplain -rw-r--r--pxa-clock.h1715logplain -rw-r--r--qcom,gcc-apq8084.h12872logplain -rw-r--r--qcom,gcc-ipq4019.h5423logplain -rw-r--r--qcom,gcc-ipq806x.h8574logplain -rw-r--r--qcom,gcc-mdm9615.h9497logplain -rw-r--r--qcom,gcc-msm8660.h7932logplain -rw-r--r--qcom,gcc-msm8916.h6190logplain -rw-r--r--qcom,gcc-msm8960.h9342logplain -rw-r--r--qcom,gcc-msm8974.h12340logplain -rw-r--r--qcom,gcc-msm8994.h4858logplain -rw-r--r--qcom,gcc-msm8996.h12575logplain -rw-r--r--qcom,lcc-ipq806x.h899logplain -rw-r--r--qcom,lcc-mdm9615.h1701logplain -rw-r--r--qcom,lcc-msm8960.h1616logplain -rw-r--r--qcom,mmcc-apq8084.h5722logplain -rw-r--r--qcom,mmcc-msm8960.h4109logplain -rw-r--r--qcom,mmcc-msm8974.h5223logplain -rw-r--r--qcom,mmcc-msm8996.h9403logplain -rw-r--r--qcom,rpmcc.h2101logplain -rw-r--r--r7s72100-clock.h1218logplain -rw-r--r--r8a73a4-clock.h1596logplain -rw-r--r--r8a7740-clock.h1992logplain -rw-r--r--r8a7743-cpg-mssr.h1269logplain -rw-r--r--r8a7745-cpg-mssr.h1298logplain -rw-r--r--r8a7778-clock.h1855logplain -rw-r--r--r8a7779-clock.h1647logplain -rw-r--r--r8a7790-clock.h4367logplain -rw-r--r--r8a7791-clock.h4388logplain -rw-r--r--r8a7792-clock.h2562logplain -rw-r--r--r8a7793-clock.h4561logplain -rw-r--r--r8a7794-clock.h3679logplain -rw-r--r--r8a7795-cpg-mssr.h1890logplain -rw-r--r--r8a7796-cpg-mssr.h2066logplain -rw-r--r--renesas-cpg-mssr.h542logplain -rw-r--r--rk1108-cru.h6605logplain -rw-r--r--rk3036-cru.h4584logplain -rw-r--r--rk3066a-cru.h1068logplain -rw-r--r--rk3188-cru-common.h6105logplain -rw-r--r--rk3188-cru.h1435logplain