/* * wm8770.h -- WM8770 ASoC driver * * Copyright 2010 Wolfson Microelectronics plc * * Author: Dimitris Papastamos * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef _WM8770_H #define _WM8770_H /* Registers */ #define WM8770_VOUT1LVOL 0 #define WM8770_VOUT1RVOL 0x1 #define WM8770_VOUT2LVOL 0x2 #define WM8770_VOUT2RVOL 0x3 #define WM8770_VOUT3LVOL 0x4 #define WM8770_VOUT3RVOL 0x5 #define WM8770_VOUT4LVOL 0x6 #define WM8770_VOUT4RVOL 0x7 #define WM8770_MSALGVOL 0x8 #define WM8770_DAC1LVOL 0x9 #define WM8770_DAC1RVOL 0xa #define WM8770_DAC2LVOL 0xb #define WM8770_DAC2RVOL 0xc #define WM8770_DAC3LVOL 0xd #define WM8770_DAC3RVOL 0xe #define WM8770_DAC4LVOL 0xf #define WM8770_DAC4RVOL 0x10 #define WM8770_MSDIGVOL 0x11 #define WM8770_DACPHASE 0x12 #define WM8770_DACCTRL1 0x13 #define WM8770_DACMUTE 0x14 #define WM8770_DACCTRL2 0x15 #define WM8770_IFACECTRL 0x16 #define WM8770_MSTRCTRL 0x17 #define WM8770_PWDNCTRL 0x18 #define WM8770_ADCLCTRL 0x19 #define WM8770_ADCRCTRL 0x1a #define WM8770_ADCMUX 0x1b #define WM8770_OUTMUX1 0x1c #define WM8770_OUTMUX2 0x1d #define WM8770_RESET 0x31 #define WM8770_CACHEREGNUM 0x20 #endif ude/trace/events/cpuhp.h?id=c26665ab5c49ad3e142e0f054ca3204f259ba09c'>treecommitdiff
path: root/include/trace/events/cpuhp.h
diff options
context:
space:
mode:
authorBorislav Petkov <bp@suse.de>2017-01-20 21:29:40 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-23 09:39:55 +0100
commitc26665ab5c49ad3e142e0f054ca3204f259ba09c (patch)
tree3bab11918e18e9d25ef7544dba05cdf39d1abec5 /include/trace/events/cpuhp.h
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in the initrd since the first AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/trace/events/cpuhp.h')