/* * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver * * Copyright (c) 2012 Lucas Stach * * Partly based on code copyright/by: * * Copyright (c) 2011,2012 Toradex Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * */ #ifndef __TEGRA20_AC97_H__ #define __TEGRA20_AC97_H__ #include "tegra_pcm.h" #define TEGRA20_AC97_CTRL 0x00 #define TEGRA20_AC97_CMD 0x04 #define TEGRA20_AC97_STATUS1 0x08 /* ... */ #define TEGRA20_AC97_FIFO1_SCR 0x1c /* ... */ #define TEGRA20_AC97_FIFO_TX1 0x40 #define TEGRA20_AC97_FIFO_RX1 0x80 /* TEGRA20_AC97_CTRL */ #define TEGRA20_AC97_CTRL_STM2_EN (1 << 16) #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11) #define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10) #define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9) #define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8) #define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7) #define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6) #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5) #define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4) #define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3) #define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2) #define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1) #define TEGRA20_AC97_CTRL_STM_EN (1 << 0) /* TEGRA20_AC97_CMD */ #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24 #define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8 #define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) #define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2 #define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT) #define TEGRA20_AC97_CMD_BUSY (1 << 0) /* TEGRA20_AC97_STATUS1 */ #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24 #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT) #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8 #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT) #define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2) #define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1) #define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0) /* TEGRA20_AC97_FIFO1_SCR */ #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27 #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT) #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22 #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT) #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19) #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18) #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17) #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16) #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15) #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14) #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13) #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12) #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11) #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10) #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9) #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8) struct tegra20_ac97 { struct clk *clk_ac97; struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data; struct regmap *regmap; int reset_gpio; int sync_gpio; }; #endif /* __TEGRA20_AC97_H__ */ option>space:mode:
authorDexuan Cui <decui@microsoft.com>2017-01-28 11:46:02 -0700
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-01-31 10:59:48 +0100
commit433e19cf33d34bb6751c874a9c00980552fe508c (patch)
treece6547ef2987fbb289fa28f03536328a42781651 /sound/soc/codecs/tlv320aic23-spi.c
parent191e885a2e130e639bb0c8ee350d7047294f2ce6 (diff)
Drivers: hv: vmbus: finally fix hv_need_to_signal_on_read()
Commit a389fcfd2cb5 ("Drivers: hv: vmbus: Fix signaling logic in hv_need_to_signal_on_read()") added the proper mb(), but removed the test "prev_write_sz < pending_sz" when making the signal decision. As a result, the guest can signal the host unnecessarily, and then the host can throttle the guest because the host thinks the guest is buggy or malicious; finally the user running stress test can perceive intermittent freeze of the guest. This patch brings back the test, and properly handles the in-place consumption APIs used by NetVSC (see get_next_pkt_raw(), put_pkt_raw() and commit_rd_index()). Fixes: a389fcfd2cb5 ("Drivers: hv: vmbus: Fix signaling logic in hv_need_to_signal_on_read()") Signed-off-by: Dexuan Cui <decui@microsoft.com> Reported-by: Rolf Neugebauer <rolf.neugebauer@docker.com> Tested-by: Rolf Neugebauer <rolf.neugebauer@docker.com> Cc: "K. Y. Srinivasan" <kys@microsoft.com> Cc: Haiyang Zhang <haiyangz@microsoft.com> Cc: Stephen Hemminger <sthemmin@microsoft.com> Cc: <stable@vger.kernel.org> Signed-off-by: K. Y. Srinivasan <kys@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'sound/soc/codecs/tlv320aic23-spi.c')