/* * tegra20_das.h - Definitions for Tegra20 DAS driver * * Author: Stephen Warren * Copyright (C) 2010,2012 - NVIDIA, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA * 02110-1301 USA * */ #ifndef __TEGRA20_DAS_H__ #define __TEGRA20_DAS_H__ /* Register TEGRA20_DAS_DAP_CTRL_SEL */ #define TEGRA20_DAS_DAP_CTRL_SEL 0x00 #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5 #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5 /* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */ #define TEGRA20_DAS_DAP_SEL_DAC1 0 #define TEGRA20_DAS_DAP_SEL_DAC2 1 #define TEGRA20_DAS_DAP_SEL_DAC3 2 #define TEGRA20_DAS_DAP_SEL_DAP1 16 #define TEGRA20_DAS_DAP_SEL_DAP2 17 #define TEGRA20_DAS_DAP_SEL_DAP3 18 #define TEGRA20_DAS_DAP_SEL_DAP4 19 #define TEGRA20_DAS_DAP_SEL_DAP5 20 /* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */ #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4 /* * Values for: * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL */ #define TEGRA20_DAS_DAC_SEL_DAP1 0 #define TEGRA20_DAS_DAC_SEL_DAP2 1 #define TEGRA20_DAS_DAC_SEL_DAP3 2 #define TEGRA20_DAS_DAC_SEL_DAP4 3 #define TEGRA20_DAS_DAC_SEL_DAP5 4 /* * Names/IDs of the DACs/DAPs. */ #define TEGRA20_DAS_DAP_ID_1 0 #define TEGRA20_DAS_DAP_ID_2 1 #define TEGRA20_DAS_DAP_ID_3 2 #define TEGRA20_DAS_DAP_ID_4 3 #define TEGRA20_DAS_DAP_ID_5 4 #define TEGRA20_DAS_DAC_ID_1 0 #define TEGRA20_DAS_DAC_ID_2 1 #define TEGRA20_DAS_DAC_ID_3 2 struct tegra20_das { struct device *dev; struct regmap *regmap; }; /* * Terminology: * DAS: Digital audio switch (HW module controlled by this driver) * DAP: Digital audio port (port/pins on Tegra device) * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere) * * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific * DAC, or another DAP. When DAPs are connected, one must be the master and * one the slave. Each DAC allows selection of a specific DAP for input, to * cater for the case where N DAPs are connected to 1 DAC for broadcast * output. * * This driver is dumb; no attempt is made to ensure that a valid routing * configuration is programmed. */ /* * Connect a DAP to to a DAC * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_* * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC* */ extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel); /* * Connect a DAP to to another DAP * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_* * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP* * master: Is this DAP the master (1) or slave (0) * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0) * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0) */ extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel, int master, int sdata1rx, int sdata2rx); /* * Connect a DAC's input to a DAP * (DAC outputs are selected by the DAP) * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_* * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP* */ extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel); #endif it();'>mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2017-01-27 12:29:30 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2017-01-27 12:29:30 -0800
commitdd3b9f25c867cb2507a45e436d6ede8eb08e7b05 (patch)
tree1ec6c08cd75610083d117a2c8d5eb0829e65f33e /sound/oss/dmasound/dmasound.h
parent69978aa0f21f43529e11f924504dadb6ce2f229a (diff)
parentb4cfe3971f6eab542dd7ecc398bfa1aeec889934 (diff)
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
Pull rdma fixes from Doug Ledford: "Second round of -rc fixes for 4.10. This -rc cycle has been slow for the rdma subsystem. I had already sent you the first batch before the Holiday break. After that, we kept only getting a few here or there. Up until this week, when I got a drop of 13 to one driver (qedr). So, here's the -rc patches I have. I currently have none held in reserve, so unless something new comes in, this is it until the next merge window opens. Summary: - series of iw_cxgb4 fixes to make it work with the drain cq API - one or two patches each to: srp, iser, cxgb3, vmw_pvrdma, umem, rxe, and ipoib - one big series (13 patches) for the new qedr driver" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: (27 commits) RDMA/cma: Fix unknown symbol when CONFIG_IPV6 is not enabled IB/rxe: Prevent from completer to operate on non valid QP IB/rxe: Fix rxe dev insertion to rxe_dev_list IB/umem: Release pid in error and ODP flow RDMA/qedr: Dispatch port active event from qedr_add RDMA/qedr: Fix and simplify memory leak in PD alloc RDMA/qedr: Fix RDMA CM loopback RDMA/qedr: Fix formatting RDMA/qedr: Mark three functions as static RDMA/qedr: Don't reset QP when queues aren't flushed RDMA/qedr: Don't spam dmesg if QP is in error state RDMA/qedr: Remove CQ spinlock from CM completion handlers RDMA/qedr: Return max inline data in QP query result RDMA/qedr: Return success when not changing QP state RDMA/qedr: Add uapi header qedr-abi.h RDMA/qedr: Fix MTU returned from QP query RDMA/core: Add the function ib_mtu_int_to_enum IB/vmw_pvrdma: Fix incorrect cleanup on pvrdma_pci_probe error path IB/vmw_pvrdma: Don't leak info from alloc_ucontext IB/cxgb3: fix misspelling in header guard ...
Diffstat (limited to 'sound/oss/dmasound/dmasound.h')