#!/usr/bin/env python import os from optparse import OptionParser parser = OptionParser() parser.add_option("-v", "--verbose", dest="verbose", help="print verbose messages. Try -vv, -vvv for \ more verbose messages", action="count") (options, args) = parser.parse_args() verbose = 0 if options.verbose is not None: verbose = options.verbose vmbus_sys_path = '/sys/bus/vmbus/devices' if not os.path.isdir(vmbus_sys_path): print "%s doesn't exist: exiting..." % vmbus_sys_path exit(-1) vmbus_dev_dict = { '{0e0b6031-5213-4934-818b-38d90ced39db}' : '[Operating system shutdown]', '{9527e630-d0ae-497b-adce-e80ab0175caf}' : '[Time Synchronization]', '{57164f39-9115-4e78-ab55-382f3bd5422d}' : '[Heartbeat]', '{a9a0f4e7-5a45-4d96-b827-8a841e8c03e6}' : '[Data Exchange]', '{35fa2e29-ea23-4236-96ae-3a6ebacba440}' : '[Backup (volume checkpoint)]', '{34d14be3-dee4-41c8-9ae7-6b174977c192}' : '[Guest services]', '{525074dc-8985-46e2-8057-a307dc18a502}' : '[Dynamic Memory]', '{cfa8b69e-5b4a-4cc0-b98b-8ba1a1f3f95a}' : 'Synthetic mouse', '{f912ad6d-2b17-48ea-bd65-f927a61c7684}' : 'Synthetic keyboard', '{da0a7802-e377-4aac-8e77-0558eb1073f8}' : 'Synthetic framebuffer adapter', '{f8615163-df3e-46c5-913f-f2d2f965ed0e}' : 'Synthetic network adapter', '{32412632-86cb-44a2-9b5c-50d1417354f5}' : 'Synthetic IDE Controller', '{ba6163d9-04a1-4d29-b605-72e2ffb1dc7f}' : 'Synthetic SCSI Controller', '{2f9bcc4a-0069-4af3-b76b-6fd0be528cda}' : 'Synthetic fiber channel adapter', '{8c2eaf3d-32a7-4b09-ab99-bd1f1c86b501}' : 'Synthetic RDMA adapter', '{44c4f61d-4444-4400-9d52-802e27ede19f}' : 'PCI Express pass-through', '{276aacf4-ac15-426c-98dd-7521ad3f01fe}' : '[Reserved system device]', '{f8e65716-3cb3-4a06-9a60-1889c5cccab5}' : '[Reserved system device]', '{3375baf4-9e15-4b30-b765-67acb10d607b}' : '[Reserved system device]', } def get_vmbus_dev_attr(dev_name, attr): try: f = open('%s/%s/%s' % (vmbus_sys_path, dev_name, attr), 'r') lines = f.readlines() f.close() except IOError: lines = [] return lines class VMBus_Dev: pass vmbus_dev_list = [] for f in os.listdir(vmbus_sys_path): vmbus_id = get_vmbus_dev_attr(f, 'id')[0].strip() class_id = get_vmbus_dev_attr(f, 'class_id')[0].strip() device_id = get_vmbus_dev_attr(f, 'device_id')[0].strip() dev_desc = vmbus_dev_dict.get(class_id, 'Unknown') chn_vp_mapping = get_vmbus_dev_attr(f, 'channel_vp_mapping') chn_vp_mapping = [c.strip() for c in chn_vp_mapping] chn_vp_mapping = sorted(chn_vp_mapping, key = lambda c : int(c.split(':')[0])) chn_vp_mapping = ['\tRel_ID=%s, target_cpu=%s' % (c.split(':')[0], c.split(':')[1]) for c in chn_vp_mapping] d = VMBus_Dev() d.sysfs_path = '%s/%s' % (vmbus_sys_path, f) d.vmbus_id = vmbus_id d.class_id = class_id d.device_id = device_id d.dev_desc = dev_desc d.chn_vp_mapping = '\n'.join(chn_vp_mapping) if d.chn_vp_mapping: d.chn_vp_mapping += '\n' vmbus_dev_list.append(d) vmbus_dev_list = sorted(vmbus_dev_list, key = lambda d : int(d.vmbus_id)) format0 = '%2s: %s' format1 = '%2s: Class_ID = %s - %s\n%s' format2 = '%2s: Class_ID = %s - %s\n\tDevice_ID = %s\n\tSysfs path: %s\n%s' for d in vmbus_dev_list: if verbose == 0: print ('VMBUS ID ' + format0) % (d.vmbus_id, d.dev_desc) elif verbose == 1: print ('VMBUS ID ' + format1) % \ (d.vmbus_id, d.class_id, d.dev_desc, d.chn_vp_mapping) else: print ('VMBUS ID ' + format2) % \ (d.vmbus_id, d.class_id, d.dev_desc, \ d.device_id, d.sysfs_path, d.chn_vp_mapping) option value='35'>35space:mode:
authorBjorn Helgaas <bhelgaas@google.com>2017-01-11 09:11:53 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-11 09:11:53 -0600
commit51ebfc92b72b4f7dac1ab45683bf56741e454b8c (patch)
tree41bcd7dcfb9fcc7bbd427b2c8e070c6f33fcd1b7
parent89e9f7bcd8744ea25fcf0ac671b8d72c10d7d790 (diff)
PCI: Enumerate switches below PCI-to-PCIe bridges
A PCI-to-PCIe bridge (a "reverse bridge") has a PCI or PCI-X primary interface and a PCI Express secondary interface. The PCIe interface is a Downstream Port that originates a Link. See the "PCI Express to PCI/PCI-X Bridge Specification", rev 1.0, sections 1.2 and A.6. The bug report below involves a PCI-to-PCIe bridge and a PCIe switch below the bridge: 00:1e.0 Intel 82801 PCI Bridge to [bus 01-0a] 01:00.0 Pericom PI7C9X111SL PCIe-to-PCI Reversible Bridge to [bus 02-0a] 02:00.0 Pericom Device 8608 [PCIe Upstream Port] to [bus 03-0a] 03:01.0 Pericom Device 8608 [PCIe Downstream Port] to [bus 0a] 01:00.0 is configured as a PCI-to-PCIe bridge (despite the name printed by lspci). As we traverse a PCIe hierarchy, device connections alternate between PCIe Links and internal Switch logic. Previously we did not recognize that 01:00.0 had a secondary link, so we thought the 02:00.0 Upstream Port *did* have a secondary link. In fact, it's the other way around: 01:00.0 has a secondary link, and 02:00.0 has internal Switch logic on its secondary side. When we thought 02:00.0 had a secondary link, the pci_scan_slot() -> only_one_child() path assumed 02:00.0 could have only one child, so 03:00.0 was the only possible downstream device. But 03:00.0 doesn't exist, so we didn't look for any other devices on bus 03. Booting with "pci=pcie_scan_all" is a workaround, but we don't want users to have to do that. Recognize that PCI-to-PCIe bridges originate links on their secondary interfaces. Link: https://bugzilla.kernel.org/show_bug.cgi?id=189361 Fixes: d0751b98dfa3 ("PCI: Add dev->has_secondary_link to track downstream PCIe links") Tested-by: Blake Moore <blake.moore@men.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
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