#ifndef REMOTE_UNWIND_LIBUNWIND #include #include #include "perf_regs.h" #include "../../util/unwind.h" #include "../../util/debug.h" #endif #ifdef HAVE_ARCH_X86_64_SUPPORT int LIBUNWIND__ARCH_REG_ID(int regnum) { int id; switch (regnum) { case UNW_X86_64_RAX: id = PERF_REG_X86_AX; break; case UNW_X86_64_RDX: id = PERF_REG_X86_DX; break; case UNW_X86_64_RCX: id = PERF_REG_X86_CX; break; case UNW_X86_64_RBX: id = PERF_REG_X86_BX; break; case UNW_X86_64_RSI: id = PERF_REG_X86_SI; break; case UNW_X86_64_RDI: id = PERF_REG_X86_DI; break; case UNW_X86_64_RBP: id = PERF_REG_X86_BP; break; case UNW_X86_64_RSP: id = PERF_REG_X86_SP; break; case UNW_X86_64_R8: id = PERF_REG_X86_R8; break; case UNW_X86_64_R9: id = PERF_REG_X86_R9; break; case UNW_X86_64_R10: id = PERF_REG_X86_R10; break; case UNW_X86_64_R11: id = PERF_REG_X86_R11; break; case UNW_X86_64_R12: id = PERF_REG_X86_R12; break; case UNW_X86_64_R13: id = PERF_REG_X86_R13; break; case UNW_X86_64_R14: id = PERF_REG_X86_R14; break; case UNW_X86_64_R15: id = PERF_REG_X86_R15; break; case UNW_X86_64_RIP: id = PERF_REG_X86_IP; break; default: pr_err("unwind: invalid reg id %d\n", regnum); return -EINVAL; } return id; } #else int LIBUNWIND__ARCH_REG_ID(int regnum) { int id; switch (regnum) { case UNW_X86_EAX: id = PERF_REG_X86_AX; break; case UNW_X86_EDX: id = PERF_REG_X86_DX; break; case UNW_X86_ECX: id = PERF_REG_X86_CX; break; case UNW_X86_EBX: id = PERF_REG_X86_BX; break; case UNW_X86_ESI: id = PERF_REG_X86_SI; break; case UNW_X86_EDI: id = PERF_REG_X86_DI; break; case UNW_X86_EBP: id = PERF_REG_X86_BP; break; case UNW_X86_ESP: id = PERF_REG_X86_SP; break; case UNW_X86_EIP: id = PERF_REG_X86_IP; break; default: pr_err("unwind: invalid reg id %d\n", regnum); return -EINVAL; } return id; } #endif /* HAVE_ARCH_X86_64_SUPPORT */ -next.git/commit/tools/perf/arch/arm64/tests/regs_load.S?id=c26665ab5c49ad3e142e0f054ca3204f259ba09c'>commitdiff
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authorBorislav Petkov <bp@suse.de>2017-01-20 21:29:40 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-23 09:39:55 +0100
commitc26665ab5c49ad3e142e0f054ca3204f259ba09c (patch)
tree3bab11918e18e9d25ef7544dba05cdf39d1abec5 /tools/perf/arch/arm64/tests/regs_load.S
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in the initrd since the first AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'tools/perf/arch/arm64/tests/regs_load.S')